FMU

FMU
Description	Multiply floating accumulator
Format	FMU <addr. mode> <disp.>
Code	110 0008
Affected	T A D, TG
Type	User
Architecture	ND-100, ND-110

FMU is an assembly instruction. The contents of the effective address and the following one or two locations are multiplied with the floating accumulator with the result in the floating accumulator (T A D).

On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three (ea and ea+1).

Flags affected

The rounding indicator for floating point operations (TG, sometimes called just G) may be set by this instruction.

References

• Norsk Data Document ND–06.014.02 ND-100 REFERENCE MANUAL Page 3-23
• Norsk Data Document ND–06.029.01 ND-110 Instruction Set Pages 69 and 72