ND-120 CPU

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Overview

The ND-120/CX CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip).

The designers was Lasse Bockelie and Chris Cherrington.

Introduction

The ND-120/CX is an improvement over the ND-110_CPU in a number of areas.

• Finally, the CPU board has an UART with RS-232 interface. Up until now all the ND CPU's used current-loop interface.
• Onboard memory up to 6MB.
• The ND-120/CX CPU is a high-speed version (approximately 1.9 times faster) of the ND-110/CX CPU.
• The ND-120 CPU is upwards compatible with the ND-110 and ND-100 CPUs.
• The CPU
  • In the ND-110 the CPU is constructed from three VLSI gate arrays (RMIC, RMAC and BUFALU).
  • In the ND-120 the CPU is constructed from one big VLSI gate array, the CPU Gate Array (CGA)
    • The ND-120 has a helper chip, the DELILAH Decoding Logic Gate Array (DGA). It was produced by NEC.
  • There is an onboard 68705U3 CPU/Microcontroller on the CPU board, for Panel Control and real-time clock.
• Cycle Control:
  • The cycle controller, which defines the timing sequence in executing microinstructions, operates differently in the ND-120 compared to the ND-110.

• Microcache:
  • The ND-110 has a 2K long instruction cache and microcache address area occupying the top 2K in control store.
  • The ND-120, in contrast, has a 1K long instruction cache and microcache address area occupying the top 1K in control store.
  • In ND-120, the address range 6—7K is not required for microcache, and may be used as a further 1K of extension area.

Print versions

• 3202 - The development phase used board revisions A, B and C
• 3202 - The final revision was D. The design documents dates this revision to 5/10/1987.

Macrocode

There doesnt seem to be any new macrocode opcodes in the ND-120/CX vs the ND-110/CX.

Microcode

The microcode is very similar to the microcode in the ND-110 except a few changes. And most of the changes seems to be related to the change of the UART.

Summary:

• For the ND-110, bits 21-27 of the microinstruction word are inverted after assembly. This has been fixed for the ND-120.
• Bit 21 has been renamed to DLY from DELAY to accord with revised timing delay function.
• Bits 32-36 (Command field):
  • Changed Command 5
    • In ND-110, 'RSDA' - Reset the data available signal from UART.
    • In the ND-120, the command 'CEUART' depends on the value in MIS field (MIS1 and MIS0)
      • 05,0 - UART data (r/w data)
      • 05,1 - UART status (r/w status)
      • 05,2 - UART mode (r/w mode)
      • 05,3 - UART comm (r/w comm)
      • See the datasheet on the 2661 UART device for further details:
        • https://datasheetspdf.com/pdf-file/1412058/SMSC/COM2661-3/1
        • https://bitsavers.org/components/microchipTechnology/_dataBooks/1990_Microchip_Data_Book.pdf
  • New Command 36.2 : LCS (Load Command Store) - The whole of the control store is loaded from Control Store PROM to Control Store RAM
  • New Command 36.3 : XSLOW - In ND-120, force current microcycle to the maximum length of time (435.2ns). This is used for very slow I/O devices e.g. the UART
  • Changed Command 06,0
    • In ND-110, 'TBSTR' - Transmit Data Strobe command to the UART on the PCU card
    • In ND-120, 'spare'
  • Changed Command 10 SLOW (Command a "slow" microcycle)
    • In ND-110 a slow microcycle is 256ns
    • In ND-120 a slow microcycle is a minimum (no wait states) of 204.8ns

• Bits 37-41 (IDBS - Internal Data Bus Source)
  • IDBS 34 - In ND-110 this was 'JMPA', in ND-120 this is a 'spare'
  • IDBS 36 - In ND-110 this was a 'spare', in ND-120 this is 'PICMASK" (Read PIC mask register)
  • IDBS 37 - In ND-110 this was a 'spare', in ND-120 this is 'UART' (For reading from UART. See also command decode 5.x CEUART)

For more details check out the "ND-06.031.1 EN ND-110 and ND-120 Microprogrammer's Guide" document.[1]

A scanned source of the the Microcode and a dump of the EPROM's from an ND-120/CX CPU version L is available

• Source listing and binary dump : Microcode Version L

Design documents

• Root folder: GitHub

• All the original design documents: Design Documents PDF files

• Logisim Schematics re-created from design documents: Logisim CIRC files

• Verilog code from converted Logisim Schemathics : Verilog Files

There is also a copy of the scanned design document PDF's at norsk-data.com:

• Circuit Diagrams Access the Circuit Diagrams
• Introduction to Hardware View the Hardware Introduction
• Design Documentation Read the Design Documentation
• Schematics Explore the Schematics

Training videos

• ND-120 - DELILAH - Hardware Introduction - Part 1 of 2 YouTube

The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip). This is part 1 of 2 - with Lasse Bockelie from February 1987

• ND-120 - DELILAH - Hardware Introduction - Part 2 of 2 YouTube

The ND-120 CPU was a complete reimplementation on an LSI chip (The so-called Delilah chip). This is part 2 of 2 - with Chris Cherrington from February 1987