ND-06.015

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ND-06.015 ND-100 FUNCTIONAL DESCRIPTION

Description of the main building blocks of the ND-100 and their functions from a hardware point of view. Written for technical and maintenance personnel.

The manual contains a lot of technical information, from signals on the ND-100 bus to programming instructions fore some IO cards.

340 Pages.

Table of contents

1     ND-100 Architecture
1.1     Introduction
1.2     The Instruction Set
1.3     Addressing Modes
1.4     The Bus Structure
1.5     Functional Modules
1.5.1     General
1.5.2     The Central Processing Unit (CPU) Module
1.5.3     The Memory Management System
1.5.4     The Memory System
1.5.5     The Input/Output System
1.6     The ND Cabinets
1.6.1     The Small Cabinet
1.6.2     The Large Cabinet
2     Central processor
2.1     General
2.2     Internal communication
2.3     Fundamental building blocks
2.3.1     General Considerations
2.3.2     Instruction Execution Overview
2.4     Instruction fetch and execution
2.4.1     Instruction Readout
2.4.2     Prefetch
2.4.3     Instruction Execution
2.5     The Register file
2.5.1     The 8 Working Registers
2.5.2     Status Indicators
2.6     Microprogram sequencer
2.6.1     General
2.6.1     The Microprogram Sequencer
2.6.1     Sequencing
2.6.1     Functional Flow
2.7     Pipeline
2.8     The Arithmetic Logic Unit
2.8.1     General
2.8.2     The ALU Bit Slice
2.9     The Interrupt system
2.9.1     General
2.9.1.1     Polling
2.9.1.2     Interrupts
2.9.2     ND-100 Interrupt System
2.9.2.1     General
2.9.2.2     Functional Operation
2.9.2.3     The External Interrupt System
2.9.2.3.1     External Interrupt Identification
2.9.2.4     The Internal Interrupt System
2.9.2.4.1     Internal Hardware Status Interrupt
2.9.2.4.2     Internal Interrupt Identification
2.9.2.5     Programming Control of the Interrupt System
2.9.2.5.1     Control of the Interrupt System
2.9.2.5.2     Programming the Interrupt Register
2.9.2.5.3     Leaving the Interrupt Level
2.9.2.5.4     Use of the PVL Register
2.9.2.6     Initializing the Interrupt System
2.10    The Address arithmetic
2.10.1    General
2.10.2    Addressing Structure
2.10.3    Principles of Address Arithmetic
3     The Memory management system
3.1     General
3.2     Implementation
3.2.1     The Paging and Protection System
3.2.2     CPU Connection
3.2.3     Memory Management Architecture
3.3     Address Translation
3.3.1     Virtual to Physical Address Mapping
3.3.2     Page Table Selection
3.3.3     Page Table Assignment
3.4     Memory Protection System
3.4.1     General
3.4.2     Layout of Page Tables
3.4.3     Page Protection System
3.4.4     Ring Protection System
3.4.4.1     General
3.4.4.2     User
3.4.4.3     User Ring
3.4.4.4     Program
3.4.4.5     Program Ring
3.4.4.6     Ring Usage
3.4.4.7     Ring Assignment
3.4.5     Privileged Instructions
3.4.6     Page Used and Written in Page
3.5     Memory Management Control and Status
3.5.1     The PON and POF Instructions
3.5.2     The SEX and REX Instructions
3.5.3     Paging Control Register
3.5.4     Paging Status Register
3.6     Control of Page Tables
3.6.1     General
3.6.2     Shadow Memory
3.6.3     Reading and Writing in Page Tables
3.7     Timing
3.8     Examples
4     ND-100 Bus system
4.1     General
4.2     Bus Control
4.3     Physical Arrangement of the ND-100 Bus
4.4     Organisation of ND-100 Modules
4.5     Bus Timing Considerations
5     The ND-100 Storage system
5.1     General
5.2     The Memory Hierarchy
5.3     ND-100 Memory System
5.4     MOS Memory Operation Principle
5.4.1     General
5.4.2     A Memory Cell
5.4.3     16 K * 1 Bit Memory Chip
5.4.3.1     Functional Operation
5.4.3.2     Read Cycle
5.4.3.3     Write Cycle
5.4.3.4     Refresh Cycle
5.5     Cache Memory
5.5.1     General
5.5.2     Cache Memory Architecture
5.5.2.1     Type
5.5.2.2     Size
5.5.2.3     Placement/Replacement Algorithm
5.5.2.4     Program Start
5.5.3     Cache Memory Organization
5.5.4     Cache Memory Access
5.5.4.1     Cache Addressing
5.5.4.2     Write Access
5.5.4.3     Read Access
5.5.5     Cache Control and Status
5.5.5.1     Cache Control
5.5.5.2     Cache Status
5.6     Local Memory
5.6.1     General
5.6.2     Memory Module Placement
5.6.2.1     The Thumbwheel settings
5.6.3     Addressing
5.6.4     Data
5.6.5     Memory Access
5.6.6     Refresh
5.7     Memory Error Check and Correction
5.7.1     General
5.7.2     Functional Description
5.7.2.1     Parity Checking
5.7.2.2     Error Correction
5.7.3     Implementation
5.8     Memory Control and Status
5.8.1     Error Correction Control Register (ECCR)
5.8.2     Memory Status Register
5.9     Error Logging
6     The Input/Output system
6.1     General
6.2     ND-100 Bus in the I/O system
6.2.1     General
6.2.2     Organization of an I/O Device Controller Module
6.2.3     Allocation of the ND-100 Bus
6.3     Programmed Input/Output - PIO
6.3.1     General
6.3.2     The Input Output/Instructions IOX and IOXT
6.3.3     The Transfer Direction
6.3.3.1     The IOX Instruction Transfer Direction
6.3.3.2     The IOXT Instruction Transfer Direction
6.3.4     Calculation of the Device Register Address
6.3.4.1     The IOX Instruction Address Range
6.3.4.2     The IOXT Instruction Address Range
6.3.4.3     Specification of an I/O Device Register Address
6.3.4.4     The Device Registers on I/O Interfaces
6.4     Control and Status Registers on ND Designed PIO and DMA Interfaces
6.4.1     General
6.4.2     Format and Function of the Control Register
6.4.3     Format and Function of the Status Register
6.5     Loading Sequence for Device Registers on I/O Interfaces
6.5.1     The Loading Sequence
6.5.2     Programming Example of a Noninterruption I/O Routine
6.6     ND-100 Bus Signals During IOX instructions
6.6.1     IOX Input
6.6.2     IOX Output
6.7     The I/O System's Connection to the Interrupt System
6.7.1     General
6.7.2     The I/O Device Controller Levels
6.7.3     Device Interrupt Identification
6.7.4     The Ident Instruction
6.7.4.1     The Ident Instruction Format
6.7.4.2     ND-100 Bus Signals During Ident Instruction
6.7.5     Programming Input/Output Using Interrupts
6.8     Direct Memory Access - DMA
6.8.1     General
6.8.2     Initialization
6.8.3     Transfer
6.8.4     Termination and Status Check
6.8.5     ND-100 Bus Signals During a DMA Transfer
6.8.5.1     DMA Input
6.8.5.2     DMA Output
6.8.6     Programming of a Direct Memory Access Channel - DMA
6.9     Programming Specifications for I/O Devices on the CPU Board
6.9.1     The Current Loop Interface
6.9.2     The Real-Time Clock
6.10    NORD-10/S modules used in ND-100
7     Operators Interaction
7.1     Control Panel Push Buttons
7.1.1     The Panel Lock Key
7.1.2     Status Indicators
7.2     MOPC Microprogrammed Operator's Communication
7.2.1     General Considerations
7.2.2     Control Functions (Do not affect display)
7.2.2.1     System Control
7.2.2.1.1     Master Clear
7.2.2.1.2     Stop
7.2.2.1.3     ALD Load
7.2.2.1.4     General Load
7.2.2.1.5     Leaving MOPC
7.2.2.2     Program Execution
7.2.2.2.1     Start Program
7.2.2.2.2     Continue a Program
7.2.2.2.3     Single Instruction
7.2.2.2.4     Instruction Breakpoint
7.2.2.2.5     Manual Instruction
7.2.2.2.6     Single I/O Instruction Function
7.2.2.3     Miscellaneous Function
7.2.2.3.1     Internal Memory Test
7.2.2.3.2     Delete Entry
7.2.2.3.3     Current Location Counter
7.2.3     Monitor Functions (Also shown on Display)
7.2.3.1     Memory Functions
7.2.3.1.1     Physical Examine Mode
7.2.3.1.2     Virtual Examine Mode
7.2.3.1.3     Memory Examine
7.2.3.1.4     Memory Deposit
7.2.3.1.5     Deposit Rules
7.2.3.1.6     Memory Dump
7.2.3.2     Register Functions
7.2.3.2.1     Register Examine
7.2.3.2.2     Register Deposit
7.2.3.2.3     Register Dump
7.2.3.2.4     User Register
7.2.3.2.5     Operator Panel 'Switches'
7.2.3.3     Internal Register Functions
7.2.3.3.1     Internal Register Examine
7.2.3.3.2     Internal Register Deposit
7.2.3.3.3     Internal register Dump
7.2.3.3.4     Scratch Register Dump
7.2.4     Display Functions (Affect only display)
7.2.4.1     Displayed Format
7.2.4.2     Display Memory Bus
7.2.4.3     Display Activity
7.2.5     Bootstrap Loaders
7.2.5.1     Binary Format Load
7.2.5.2     Mass Storage Load
7.2.5.3     Automatic Load Descriptor
7.3     The Display
7.3.1     General
7.3.2     The Different Display Functions
8     ND-100 POWER SUPPLY
8.1     Power in the Small Cabinet
8.2     Power in the Large Cabinet
8.2.1     Power Location and Distribution in the Large Cabinet
8.3     Power Fail and Automatic Restart
8.3.1     General
8.3.2     Power Fail
8.3.3     Automatic Restart
9     MISCELLANEOUS
9.1     Privileged Instructions
9.1.1     General
9.1.2     Register Block Functions
9.1.3     Inter-Level Register Instructions
9.1.4     Accumulator Transfer Instructions
9.1.5     System Control Instructions
9.1.5.1     Interrupt Control Instructions
9.1.5.2     Memory Management Control Instructions
9.1.5.3     Wait or Give Up Priority
9.1.5.4     Monitor Call Instruction
9.1.6     Input/Output Control Instructions
9.1.6.1     IOX - Input/Output Execute
9.1.6.2     Extension of the Device Register Address
9.1.7     Examine and Deposit
9.1.7.1     Examine
9.1.7.2     Deposit
9.1.8     Load Writable Control Store
9.2     Internal Registers
9.3     Writable Store
9.3.1     General
9.3.2     Writing Micro Code for Writable Control Store
9.3.3     Load the Writable Control Store
9.3.4     Customer Specified Instructions
9.4     Panel Processor Programming Specification
9.4.1     Panel Control Register
9.4.2     Panel Status Register
9.4.3     Panel Commands
9.4.3.1     Message on Function Display
9.4.3.2     Update Calendar
9.5     ND-100 Instruction Codes

Appendixes

A     ND-100 mnemonics and their octal values
B     Programming specifications for some I/O devices
B.1     ND-100 Terminal Programming Specifications
B.2     Specifications of Paper Tape Reader Interface
B.3     Specifications of the Paper Tape Punch Interface
B.4     ND-100 Floppy Disk Programming Instructions
B.4.1     Device Register Address
B.4.2     Instruction Formats and Descriptions
B.4.2.1     Read Data Buffer (IOX RDAT)
B.4.2.2     Write Data Buffer (IOX WDAT)
B.4.2.3     Read Status Register Number 1 (IOX RSR1)
B.4.2.4     Write Control Word (IOX WCWD)
B.4.2.5     Read Status Register Number 2 (IOX RSR2)
B.4.2.6     Write Drive Address/Write Difference (IOX WDAD)
B.4.2.7     Read Test Data (IOX RTST)
B.4.2.8     Write Sector/Write Test Byte (IOX WSCT)
B.5     ND-100 10 MB Disk Controller Programming Specifications
C     Standard ND-100 Device Register Addresses and IDENT Codes
D     Switch Settings for the different ND-100 Modules
D.1     Switches on the CPU Module (3002)
D.1.1     ALD - Automatic Load Descriptor
D.1.2     Console: Speed Settings for the Console Terminal
D.1.3     The Indicators (The Red and Green LEDs)
D.2     
D.2.1     
D.2.2     
D.3     
D.3.1     
D.3.2     
D.3.3     
D.4     
D.4.1     
D.4.2     
D.5     
D.6     
D.7     
D.7.1     
D.7.2     
D.7.3     
D.8     
D.8.1     
D.9     
D.9.1     
D.9.2     
D.9.3     
D.10    
D.10.1    
D.10.2    
D.11    
D.11.1    
D.11.2    
D.12    
D.12.1    
D.12.2    
D.13    
D.13.1    
D.14    
D.14.1    
D.14.2    
D.14.3    
D.14.4    
D.14.4.1    
D.14.4.2    
D.14.4.3    
D.14.5    
D.14.6    
D.14.7    
D.15    
D.15.1    
D.15.2    
D.15.3    
D.15.4    
D.16    
D.16.1    
D.16.2    
D.16.3    
D.17    
D.18    
D.18.1    
D.18.2    
D.18.3    
D.18.4    
D.18.5    
D.19    
D.19.1    
D.19.2    
D.19.3    
D.19.4    
D.19.5    
D.20    
D.20.1    
D.20.2    
D.20.3    
D.20.4    
D.20.5    
D.20.6    
D.21    
D.21.1    
D.21.2    
D.21.3    
D.22    
D.22.1    
D.22.2    
D.22.3    
D.23    
D.23.1    
D.23.2    
D.23.3    
D.24    
D.24.1    
D.24.2    
D.25    
D.25.1    
D.25.2    
D.25.3    
D.25.4    
D.25.5    
D.26    
D.26.1    
D.26.2    
D.27    
D.27.1    
D.27.1.1    
D.27.1.2    
D.27.2    
D.27.2.1    
D.27.2.2    
D.28    
D.28.1    
D.28.2    
D.28.3    
D.28.4    
D.29    
D.29.1    
D.30    
D.30.1    
D.30.2    
D.30.3    
D.31    
D.31.1    
D.31.2    
D.32    
D.32.1    
D.32.2    
D.32.3    
D.32.4    
D.33    
D.33.1    
D.33.2    
D.33.2.1    
D.33.2.2    
D.33.3    
D.33.4    
D.34    
D.34.1    
D.34.2    
D.34.3    
D.34.4    
D.35    
D.35.1     
D.35.2     
E     Microprogram-Panel Processor Communication
E.1     
E.2     
E.3     
F     Microprogrammable Registers on Memory Management
F.1     
F.2     
G     Internal Registers and their Bit Assignment
H     Operator's Communication Instruction Survey
H.1     
H.2     
H.3     
I     ND-100 Technical Specifications
I.1     
I.2     
J     ASCII character set (ANSI X3.4 1968)
      Index of abbreviations

Versions

  • ND-06.015.01 Original printing 08/1980
  • ND-06.015.02 Second version 04/1985

Known copies

A pdf copy is located on the Bitsavers website.

Related manuals

Reference

Norsk Data Document ND–06.015 ND-100 FUNCTIONAL DESCRIPTION (ND-06.015.02 1985)

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