ND-1xx Instructions: Difference between revisions
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* [[SHA]] – Shift A register | * [[SHA]] – Shift A register | ||
* [[SAD]] – Shift A and D registers connected | * [[SAD]] – Shift A and D registers connected | ||
===== Types ===== | ===== Subinstructions (Types) ===== | ||
For each shift instruction, one of the following types can be specified | For each shift instruction, one of the following types can be specified | ||
:* ''nil (default)'' Arithmetic shift | :* ''nil (default)'' Arithmetic shift | ||
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:* [[ZIN]] – Zero end input | :* [[ZIN]] – Zero end input | ||
:* [[LIN]] – Link end input | :* [[LIN]] – Link end input | ||
===== Direction ===== | ===== Subinstructions (Direction) ===== | ||
:* ''nil (default)'' Left shift | :* ''nil (default)'' Left shift | ||
:* [[SHR]] – Right shift | :* [[SHR]] – Right shift | ||
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* [[ION]] – Interrupt system on | * [[ION]] – Interrupt system on | ||
* [[LWCS]] – Load Writeable Control Store | * [[LWCS]] – Load Writeable Control Store | ||
* [[MON]] – Monitor Call | * [[MON]] – Monitor Call | ||
* [[PIOF]] – Memory management and interrupt system off | * [[PIOF]] – Memory management and interrupt system off | ||
* [[PION]] – Memory management and interrupt system on | * [[PION]] – Memory management and interrupt system on | ||
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* [[REX]] – Reset extended address mode | * [[REX]] – Reset extended address mode | ||
* [[SEX]] – Set extended address mode | * [[SEX]] – Set extended address mode | ||
* [[WAIT]] – Wait | * [[WAIT]] – Wait (give up priority) | ||
* [[OPCOM]] – Operator's Communication Code | * [[OPCOM]] – Operator's Communication Code | ||
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=== Register Operations === | === Register Operations === | ||
==== Arithmetic Operations, RAD=1: ==== | ==== Arithmetic Operations, RAD=1: ==== | ||
* [[RADD]] – Register addition | * [[RADD]] – Register addition | ||
* [[RSUB]] – Register subtraction | * [[RSUB]] – Register subtraction | ||
* [[COPY]] – Register transfer | * [[COPY]] – Register transfer | ||
===== Subinstruction ===== | ===== Subinstruction ===== | ||
* [[AD1]] – Also add 1 to destination | :* [[AD1]] – Also add 1 to destination | ||
* [[ADC]] – Also add old carry to destination | :* [[ADC]] – Also add old carry to destination | ||
==== Logical Operations, RAD=0: ==== | ==== Logical Operations, RAD=0: ==== | ||
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* [[RORA]] – Register logical OR | * [[RORA]] – Register logical OR | ||
===== Subinstruction ===== | ===== Subinstruction ===== | ||
* [[CLD]] – Clear destination register before operation | :* [[CLD]] – Clear destination register before operation | ||
* [[CM1]] – Use complement ( | :* [[CM1]] – Use complement ([[wikipedia:ones' complement|ones' complement]]) of source register as operand. | ||
==== Combined Instructions: ==== | ==== Combined Instructions: ==== | ||
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=== Floating Conversion === | === Floating Conversion === | ||
* [[NLZ]] – | * [[NLZ]] – Normalize (integer to floating) | ||
* [[DNZ]] – | * [[DNZ]] – Denormalize (floating to integer) | ||
=== Memory Examine/Deposit Instructions === | === Memory Examine/Deposit Instructions === | ||
* [[EXAM]] – | * [[EXAM]] – Memory examine | ||
* [[DEPO]] – | * [[DEPO]] – Memory deposit | ||
=== Sequencing Instructions === | === Sequencing Instructions === | ||
==== Unconditional Jump ==== | ==== Unconditional Jump ==== | ||
* [[JMP]] – | * [[JMP]] – Jump | ||
* [[JPL]] – | * [[JPL]] – Jump to subroutine | ||
==== Conditional Jump ==== | ==== Conditional Jump ==== | ||
* [[JAP]] – | * [[JAP]] – Jump if A register is positive or zero | ||
* [[JAN]] – | * [[JAN]] – Jump if A register is negative | ||
* [[JAZ]] – | * [[JAZ]] – Jump if A register is zero | ||
* [[JAF]] – | * [[JAF]] – Jump if A register is filled (not zero) | ||
* [[JXN]] – | * [[JXN]] – Jump lf X register is negative | ||
* [[ | * [[JXZ]] – Jump if X register is zero. | ||
* [[ | * [[JPC]] – Count and jump if X register is positive or zero. | ||
* [[ | * [[JNC]] – Count and jump if X register is negative. | ||
==== Skip Instructions ==== | ==== Skip Instructions ==== | ||
* [[ | * [[SKP]] – Skip next instruction if specified condition is true | ||
===== Subinstructions (Specified condition) ===== | |||
:* [[EQL]] – Equal | |||
:* [[GEQ]] – Signed greater or equal to (owerflow not OK) | |||
:* [[GRE]] – Signed greater or equal to (owerflow OK) | |||
:* [[MGRE]] – Magnitude greater or equal to | |||
:* [[UEQ]] – Unequal to | |||
:* [[LSS]] – Signed less than (owerflow not OK) | |||
:* [[LST]] – Signed less than (owerflow OK) | |||
:* [[MLST]] – Magnitude less than | |||
===== Dummys (may be used to obtain easy readability) ===== | |||
:* IF | |||
:* 0 | |||
== Sources == | == Sources == |
Revision as of 06:29, 30 March 2009
Instruction Set
Memory Reference Instructions
Store Instructions
Load Instructions
Arithmetic and Logical Instructions
- ADD – Add to A (C, O and Q may also be affected)
- SUB – Subtract from A (C, O and Q may also be affected)
- AND – Logical AND to A
- ORA – Logical inclusive OR to A
- MPY – Multiply integer (O and Q may also be affected)
Double Word Instructions
Floating Instructions
- LDF – Load floating accumulator
- STF – Store floating accumulator
- FAD – Add to floating accumulator (C may also be affected)
- FSB – Subtract from floating accumulator (C may also be affected)
- FMU – Multiply floating accumulator (C may also be affected)
- FDV – Divide floating accumulator (Z and C may also be affected)
Byte Instructions
Execute Instruction
- EXR – Execute instruction found in specified register
Bit Instructions
- BSKP – Skip next location if specified condition is true
- BSET – Set specified bit equal to specified condition
- BSTA – Store and clear K
- BSTC – Store complement and set K
- BLDA – load K
- BLDC – Load bit complement to K
- BANC – Logical AND with bit complement
- BORC – Logical OR with bit complement
- BAND – Logical AND to K
- BORA – Logical OR to K
Shift Instructions
- SHT – Shift T register
- SHD – Shift D register
- SHA – Shift A register
- SAD – Shift A and D registers connected
Subinstructions (Types)
For each shift instruction, one of the following types can be specified
Subinstructions (Direction)
- nil (default) Left shift
- SHR – Right shift
System Control Instructions
- IOF – Interrupt system off
- ION – Interrupt system on
- LWCS – Load Writeable Control Store
- MON – Monitor Call
- PIOF – Memory management and interrupt system off
- PION – Memory management and interrupt system on
- POF – Memory management off
- PON – Memory management on
- REX – Reset extended address mode
- SEX – Set extended address mode
- WAIT – Wait (give up priority)
- OPCOM – Operator's Communication Code
Transfer Instructions
Load Independent Instructions
Inter-level Instructions
Register Operations
Arithmetic Operations, RAD=1:
Subinstruction
Logical Operations, RAD=0:
- SWAP – Register exchange
- RAND – Register logical AND
- REXO – Register logical exclusive OR
- RORA – Register logical OR
Subinstruction
- CLD – Clear destination register before operation
- CM1 – Use complement (ones' complement) of source register as operand.
Combined Instructions:
- EXIT – Return from subroutine
- RCLR – Register clear
- RINC – Register increment
- RDCR – Register decrement
Extended Arithmetic Operations:
Floating Conversion
Memory Examine/Deposit Instructions
Sequencing Instructions
Unconditional Jump
Conditional Jump
- JAP – Jump if A register is positive or zero
- JAN – Jump if A register is negative
- JAZ – Jump if A register is zero
- JAF – Jump if A register is filled (not zero)
- JXN – Jump lf X register is negative
- JXZ – Jump if X register is zero.
- JPC – Count and jump if X register is positive or zero.
- JNC – Count and jump if X register is negative.
Skip Instructions
- SKP – Skip next instruction if specified condition is true
Subinstructions (Specified condition)
Dummys (may be used to obtain easy readability)
- IF
- 0
Sources
- Norsk Data Document ND–06.014 ND-100 REFERENCE MANUAL (ND-06.014.02 rev A)
- Norsk Data Document ND–99.005 ND-100 INSTANT INSTRUCTION CODES (ND-99.005.02 12/84)