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| 1 ND-100 Architecture | | 1 ND-100 Architecture |
| 1.1 Introduction | | 1.1 Introduction |
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| J ASCII character set (ANSI X3.4 1968) | | J ASCII character set (ANSI X3.4 1968) |
| Index of abbreviations | | Index of abbreviations |
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| ==Versions== | | ==Versions== |
Revision as of 12:34, 5 November 2008
ND-06.015 ND-100 FUNCTIONAL DESCRIPTION
Description of the main building blocks of the ND-100 and their functions from a hardware point of view. Written for technical and maintenance personnel.
The manual contains a lot of technical information, from signals on the ND-100 bus to programming instructions fore some IO cards.
340 Pages.
Table of contents
1 ND-100 Architecture
1.1 Introduction
1.2 The Instruction Set
1.3 Addressing Modes
1.4 The Bus Structure
1.5 Functional Modules
1.5.1 General
1.5.2 The Central Processing Unit (CPU) Module
1.5.3 The Memory Management System
1.5.4 The Memory System
1.5.5 The Input/Output System
1.6 The ND Cabinets
1.6.1 The Small Cabinet
1.6.2 The Large Cabinet
2 Central processor
2.1 General
2.2 Internal communication
2.3 Fundamental building blocks
2.3.1 General Considerations
2.3.2 Instruction Execution Overview
2.4 Instruction fetch and execution
2.4.1 Instruction Readout
2.4.2 Prefetch
2.4.3 Instruction Execution
2.5 The Register file
2.5.1 The 8 Working Registers
2.5.2 Status Indicators
2.6 Microprogram sequencer
2.6.1 General
2.6.1 The Microprogram Sequencer
2.6.1 Sequencing
2.6.1 Functional Flow
2.7 Pipeline
2.8 The Arithmetic Logic Unit
2.8.1 General
2.8.2 The ALU Bit Slice
2.9 The Interrupt system
2.9.1 General
2.9.1.1 Polling
2.9.1.2 Interrupts
2.9.2 ND-100 Interrupt System
2.9.2.1 General
2.9.2.2 Functional Operation
2.9.2.3 The External Interrupt System
2.9.2.3.1 External Interrupt Identification
2.9.2.4 The Internal Interrupt System
2.9.2.4.1 Internal Hardware Status Interrupt
2.9.2.4.2 Internal Interrupt Identification
2.9.2.5 Programming Control of the Interrupt System
2.9.2.5.1 Control of the Interrupt System
2.9.2.5.2 Programming the Interrupt Register
2.9.2.5.3 Leaving the Interrupt Level
2.9.2.5.4 Use of the PVL Register
2.9.2.6 Initializing the Interrupt System
2.10 The Address arithmetic
2.10.1 General
2.10.2 Addressing Structure
2.10.3 Principles of Address Arithmetic
3 The Memory management system
3.1 General
3.2 Implementation
3.2.1 The Paging and Protection System
3.2.2 CPU Connection
3.2.3 Memory Management Architecture
3.3 Address Translation
3.3.1 Virtual to Physical Address Mapping
3.3.2 Page Table Selection
3.3.3 Page Table Assignment
3.4 Memory Protection System
3.4.1 General
3.4.2 Layout of Page Tables
3.4.3 Page Protection System
3.4.4 Ring Protection System
3.4.4.1 General
3.4.4.2 User
3.4.4.3 User Ring
3.4.4.4 Program
3.4.4.5 Program Ring
3.4.4.6 Ring Usage
3.4.4.7 Ring Assignment
3.4.5 Privileged Instructions
3.4.6 Page Used and Written in Page
3.5 Memory Management Control and Status
3.5.1 The PON and POF Instructions
3.5.2 The SEX and REX Instructions
3.5.3 Paging Control Register
3.5.4 Paging Status Register
3.6 Control of Page Tables
3.6.1 General
3.6.2 Shadow Memory
3.6.3 Reading and Writing in Page Tables
3.7 Timing
3.8 Examples
4 ND-100 Bus system
4.1 General
4.2 Bus Control
4.3 Physical Arrangement of the ND-100 Bus
4.4 Organisation of ND-100 Modules
4.5 Bus Timing Considerations
5 The ND-100 Storage system
5.1 General
5.2 The Memory Hierarchy
5.3 ND-100 Memory System
5.4 MOS Memory Operation Principle
5.4.1 General
5.4.2 A Memory Cell
5.4.3 16 K * 1 Bit Memory Chip
5.4.3.1 Functional Operation
5.4.3.2 Read Cycle
5.4.3.3 Write Cycle
5.4.3.4 Refresh Cycle
5.5 Cache Memory
5.5.1 General
5.5.2 Cache Memory Architecture
5.5.2.1 Type
5.5.2.2 Size
5.5.2.3 Placement/Replacement Algorithm
5.5.2.4 Program Start
5.5.3 Cache Memory Organization
5.5.4 Cache Memory Access
5.5.4.1 Cache Addressing
5.5.4.2 Write Access
5.5.4.3 Read Access
5.5.5 Cache Control and Status
5.5.5.1 Cache Control
5.5.5.2 Cache Status
5.6 Local Memory
5.6.1 General
5.6.2 Memory Module Placement
5.6.2.1 The Thumbwheel settings
5.6.3 Addressing
5.6.4 Data
5.6.5 Memory Access
5.6.6 Refresh
5.7 Memory Error Check and Correction
5.7.1 General
5.7.2 Functional Description
5.7.2.1 Parity Checking
5.7.2.2 Error Correction
5.7.3 Implementation
5.8 Memory Control and Status
5.8.1 Error Correction Control Register (ECCR)
5.8.2 Memory Status Register
5.9 Error Logging
6 The Input/Output system
6.1 General
6.2 ND-100 Bus in the I/O system
6.2.1 General
6.2.2 Organization of an I/O Device Controller Module
6.2.3 Allocation of the ND-100 Bus
6.3 Programmed Input/Output - PIO
6.3.1 General
6.3.2 The Input Output/Instructions IOX and IOXT
6.3.3 The Transfer Direction
6.3.3.1 The IOX Instruction Transfer Direction
6.3.3.2 The IOXT Instruction Transfer Direction
6.3.4 Calculation of the Device Register Address
6.3.4.1 The IOX Instruction Address Range
6.3.4.2 The IOXT Instruction Address Range
6.3.4.3 Specification of an I/O Device Register Address
6.3.4.4 The Device Registers on I/O Interfaces
6.4 Control and Status Registers on ND Designed PIO and DMA Interfaces
6.4.1 General
6.4.2 Format and Function of the Control Register
6.4.3 Format and Function of the Status Register
6.5 Loading Sequence for Device Registers on I/O Interfaces
6.5.1 The Loading Sequence
6.5.2 Programming Example of a Noninterruption I/O Routine
6.6 ND-100 Bus Signals During IOX instructions
6.6.1 IOX Input
6.6.2 IOX Output
6.7 The I/O System's Connection to the Interrupt System
6.7.1 General
6.7.2 The I/O Device Controller Levels
6.7.3 Device Interrupt Identification
6.7.4 The Ident Instruction
6.7.4.1 The Ident Instruction Format
6.7.4.2 ND-100 Bus Signals During Ident Instruction
6.7.5 Programming Input/Output Using Interrupts
6.8 Direct Memory Access - DMA
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.5.1
6.8.5.2
6.8.6
6.9 Programming specifications for I/O devices on the CPU board
6.9.1
6.9.2
6.10 NORD-10/S modules used in ND-100
7 Operators Interaction
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.1.1
7.2.2.1.2
7.2.2.1.3
7.2.2.1.4
7.2.2.1.5
7.2.2.2
7.2.2.2.1
7.2.2.2.2
7.2.2.2.3
7.2.2.2.4
7.2.2.2.5
7.2.2.2.6
7.2.2.3
7.2.2.3.1
7.2.2.3.2
7.2.2.3.3
7.2.3
7.2.3.1
7.2.3.1.1
7.2.3.1.2
7.2.3.1.3
7.2.3.1.4
7.2.3.1.5
7.2.3.1.6
7.2.3.2
7.2.3.2.1
7.2.3.2.2
7.2.3.2.3
7.2.3.2.4
7.2.3.2.5
7.2.3.3
7.2.3.3.1
7.2.3.3.2
7.2.3.3.3
7.2.3.3.4
7.2.4
7.2.4.1
7.2.4.2
7.2.4.3
7.2.5
7.2.5.1
7.2.5.2
7.2.5.3
7.3
7.3.1
7.3.2
8 ND-100 Power supply
8.1
8.2
8.2.1
8.3
8.3.1
8.3.2
8.3.3
9 Miscellaneous
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.5.1
9.1.5.2
9.1.5.3
9.1.5.4
9.1.6
9.1.6.1
9.1.6.2
9.1.7
9.1.7.1
9.1.7.2
9.1.8
9.2 Internal Registers
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.4
9.4.1
9.4.2
9.4.3
9.4.3.1
9.4.3.2
9.5
Appendixes:
A ND-100 mnemonics and their octal values
B Programming specifications for some I/O devices
B.1 ND-100 Terminal Programming Specifications
B.2 Specifications of Paper Tape Reader Interface
B.3 Specifications of the Paper Tape Punch Interface
B.4 ND-100 Floppy Disk Programming Instructions
B.4.1
B.4.2
B.4.2.1
B.4.2.2
B.4.2.3
B.4.2.4
B.4.2.5
B.4.2.6
B.4.2.7
B.4.2.8
B.5 ND-100 10 MB Disk Controller Programming Specifications
C Standard ND-100 Device Register Addresses and IDENT Codes
D Switch Settings for the different ND-100 Modules
D.1
D.1.
...
D.35
D.35.1
D.35.2
E Microprogram-Panel Processor Communication
E.1
E.2
E.3
F Microprogrammable Registers on Memory Management
F.1
F.2
G Internal Registers and their Bit Assignment
H Operator's Communication Instruction Survey
H.1
H.2
H.3
I ND-100 Technical Specifications
I.1
I.2
J ASCII character set (ANSI X3.4 1968)
Index of abbreviations
Versions
- ND-06.015.01 Original printing 08/1980
- ND-06.015.02 Second version 04/1985
Known copies
A pdf copy is located on the Bitsavers website.
Related manuals
Reference
Norsk Data Document ND–06.015 ND-100 FUNCTIONAL DESCRIPTION (ND-06.015.02 1985)