FAD: Difference between revisions

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(Add 'Flags affected' subsection)
(Made clearer)
 
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|Format=FAD ''<[[ND-100 addressing modes|addr. mode]]> <[[displacement|disp.]]>''
|Format=FAD ''<[[ND-100 addressing modes|addr. mode]]> <[[displacement|disp.]]>''
|Code=100&nbsp;000
|Code=100&nbsp;000
|Affected=T:=(ea) A=(ea+1) D=(ea+2)
|Affected=T A D, TG
|Architecture=[[ND-100]], [[ND-110 CPU|ND-110]]
|Architecture=[[ND-100]], [[ND-110 CPU|ND-110]]
}}
}}


'''FAD''' is an assembly instruction. The contents of the [[effective address]] and the following one or two locations are added to the [[floating accumulator]].  
'''FAD''' is an assembly instruction. The contents of the [[effective address]] and the following one or two locations are added to the [[floating accumulator]]. The result is in the floating accumulator.


On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked
On 32-bit floating point hardware only registers '''A''' and '''D''' are used, and two address locations instead of three.
to (ea) and the D register to (ea+1).


== Flags affected ==
== Flags affected ==

Latest revision as of 10:01, 1 July 2010

FAD
Description Add to floating accumulator
Format FAD <addr. mode> <disp.>
Code 100 0008
Affected T A D, TG
Type User
Architecture ND-100, ND-110

FAD is an assembly instruction. The contents of the effective address and the following one or two locations are added to the floating accumulator. The result is in the floating accumulator.

On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three.

Flags affected

The rounding indicator for floating point operations (TG, sometimes called just G) may be set by this instruction.

References