FSB: Difference between revisions
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(FSB instruction) |
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On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked | On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked | ||
to (ea) and the D register to (ea+1). | to (ea) and the D register to (ea+1). | ||
== Flags affected == | |||
The [[rounding indicator]] for floating point operations ('''TG''', sometimes called just '''G''') may be set by this instruction. | |||
== References == | == References == | ||
Revision as of 09:29, 1 July 2010
| FSB | |
|---|---|
| Description | Subtract from floating accumulator |
| Format | FSB <addr. mode> <disp.> |
| Code | 104 0008 |
| Affected | T:=(ea) A=(ea+1) D=(ea+2) |
| Type | User |
| Architecture | ND-100, ND-110 |
FAD is an assembly instruction. The contents of the effective address and the following one or two locations are subtracted from the floating accumulator.
On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked to (ea) and the D register to (ea+1).
Flags affected
The rounding indicator for floating point operations (TG, sometimes called just G) may be set by this instruction.
References
- Norsk Data Document ND–06.014.02 ND-100 REFERENCE MANUAL Page 3-22
- Norsk Data Document ND–06.029.01 ND-110 Instruction Set Pages 68 and 72