ND-1xx Instructions: Difference between revisions
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=== Transfer Instructions === | === Transfer Instructions === | ||
==== Load Independent Instructions ==== | ==== Load Independent Instructions ==== | ||
* [[TRA]] – | * [[TRA]] – Transfer to A register | ||
* [[TRR]] – | * [[TRR]] – Transfer to register | ||
==== Inter-level Instructions ==== | ==== Inter-level Instructions ==== | ||
* [[IRR]] – | * [[IRR]] – Inter Register Read | ||
* [[IRW]] – | * [[IRW]] – Inter Register Write | ||
=== Register Operations === | === Register Operations === | ||
==== Arithmetic Operations, RAD=1: ==== | ==== Arithmetic Operations, RAD=1: ==== | ||
C,O,Q may be affected by the following operations | C,O,Q may be affected by the following operations | ||
* [[RADD]] – | * [[RADD]] – Register addition | ||
* [[RSUB]] – | * [[RSUB]] – Register subtraction | ||
* [[COPY]] – | * [[COPY]] – Register transfer | ||
* [[AD1]] – | ===== Subinstruction ===== | ||
* [[ADC]] – | * [[AD1]] – Also add 1 to destination | ||
* [[ADC]] – Also add old carry to destination | |||
==== Logical Operations, RAD=0: ==== | ==== Logical Operations, RAD=0: ==== | ||
* [[SWAP]] – | * [[SWAP]] – Register exchange | ||
* [[RAND]] – | * [[RAND]] – Register logical AND | ||
* [[REXO]] – | * [[REXO]] – Register logical exclusive OR | ||
* [[RORA]] – | * [[RORA]] – Register logical OR | ||
* [[CLD]] – | ===== Subinstruction ===== | ||
* [[CM1]] – | * [[CLD]] – Clear destination register before operation | ||
* [[CM1]] – Use complement (one's complement) of source register as operand. | |||
==== Combined Instructions: ==== | ==== Combined Instructions: ==== | ||
* [[EXIT]] – | * [[EXIT]] – Return from subroutine | ||
* [[RCLR]] – | * [[RCLR]] – Register clear | ||
* [[RINC]] – | * [[RINC]] – Register increment | ||
* [[RDCR]] – | * [[RDCR]] – Register decrement | ||
==== Extended Arithmetic Operations: ==== | ==== Extended Arithmetic Operations: ==== | ||
* [[RMPY]] – | * [[RMPY]] – Integer inter-register multiply | ||
* [[RDIV]] – | * [[RDIV]] – Integer inter-register divide | ||
=== Floating Conversion === | === Floating Conversion === |
Revision as of 15:17, 29 March 2009
Instruction Set
Memory Reference Instructions
Store Instructions
Load Instructions
Arithmetic and Logical Instructions
- ADD – Add to A (C, O and Q may also be affected)
- SUB – Subtract from A (C, O and Q may also be affected)
- AND – Logical AND to A
- ORA – Logical inclusive OR to A
- MPY – Multiply integer (O and Q may also be affected)
Double Word Instructions
Floating Instructions
- LDF – Load floating accumulator
- STF – Store floating accumulator
- FAD – Add to floating accumulator (C may also be affected)
- FSB – Subtract from floating accumulator (C may also be affected)
- FMU – Multiply floating accumulator (C may also be affected)
- FDV – Divide floating accumulator (Z and C may also be affected)
Byte Instructions
Execute Instruction
- EXR – Execute instruction found in specified register
Bit Instructions
- BSKP – Skip next location if specified condition is true
- BSET – Set specified bit equal to specified condition
- BSTA – Store and clear K
- BSTC – Store complement and set K
- BLDA – load K
- BLDC – Load bit complement to K
- BANC – Logical AND with bit complement
- BORC – Logical OR with bit complement
- BAND – Logical AND to K
- BORA – Logical OR to K
Shift Instructions
- SHT – Shift T register
- SHD – Shift D register
- SHA – Shift A register
- SAD – Shift A and D registers connected
Types
For each shift instruction, one of the following types can be specified
Direction
- nil (default) Left shift
- SHR – Right shift
System Control Instructions
- IOF – Interrupt system off
- ION – Interrupt system on
- LWCS – Load Writeable Control Store
- MON – Monitor Call
- PIOF – Memory management and interrupt system off
- PION – Memory management and interrupt system on
- POF – Memory management off
- PON – Memory management on
- REX – Reset extended address mode
- SEX – Set extended address mode
- WAIT – Wait
- OPCOM – Operator's Communication Code
Transfer Instructions
Load Independent Instructions
Inter-level Instructions
Register Operations
Arithmetic Operations, RAD=1:
C,O,Q may be affected by the following operations
Subinstruction
Logical Operations, RAD=0:
- SWAP – Register exchange
- RAND – Register logical AND
- REXO – Register logical exclusive OR
- RORA – Register logical OR
Subinstruction
- CLD – Clear destination register before operation
- CM1 – Use complement (one's complement) of source register as operand.
Combined Instructions:
- EXIT – Return from subroutine
- RCLR – Register clear
- RINC – Register increment
- RDCR – Register decrement
Extended Arithmetic Operations:
Floating Conversion
Memory Examine/Deposit Instructions
Sequencing Instructions
Unconditional Jump
Conditional Jump
Skip Instructions
- SKIP –
Sources
- Norsk Data Document ND–06.014 ND-100 REFERENCE MANUAL (ND-06.014.02 rev A)
- Norsk Data Document ND–99.005 ND-100 INSTANT INSTRUCTION CODES (ND-99.005.02 12/84)