FSB: Difference between revisions
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|Format=FSB ''<[[ND-100 addressing modes|addr. mode]]> <[[displacement|disp.]]>'' | |Format=FSB ''<[[ND-100 addressing modes|addr. mode]]> <[[displacement|disp.]]>'' | ||
|Code=104 000 | |Code=104 000 | ||
|Affected=T | |Affected=T A D, TG | ||
|Architecture=[[ND-100]], [[ND-110 CPU|ND-110]] | |Architecture=[[ND-100]], [[ND-110 CPU|ND-110]] | ||
}} | }} | ||
''' | '''FSB''' is an assembly instruction. The contents of the [[effective address]] and the following one or two locations are subtracted from the [[floating accumulator]]. The result is in the floating accumulator. | ||
On 32-bit hardware only registers A and D are used, and two address locations instead of three | On 32-bit floating point hardware only registers '''A''' and '''D''' are used, and two address locations instead of three. | ||
== Flags affected == | == Flags affected == | ||
Latest revision as of 09:58, 1 July 2010
| FSB | |
|---|---|
| Description | Subtract from floating accumulator |
| Format | FSB <addr. mode> <disp.> |
| Code | 104 0008 |
| Affected | T A D, TG |
| Type | User |
| Architecture | ND-100, ND-110 |
FSB is an assembly instruction. The contents of the effective address and the following one or two locations are subtracted from the floating accumulator. The result is in the floating accumulator.
On 32-bit floating point hardware only registers A and D are used, and two address locations instead of three.
Flags affected
The rounding indicator for floating point operations (TG, sometimes called just G) may be set by this instruction.
References
- Norsk Data Document ND–06.014.02 ND-100 REFERENCE MANUAL Page 3-22
- Norsk Data Document ND–06.029.01 ND-110 Instruction Set Pages 68 and 72