ND-1xx Instructions: Difference between revisions
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See also: [[ND-1xx Instructions Sorted Numerically]] | |||
== Instruction Set == | == Instruction Set == | ||
NORD-10/ND-100/ND-120 instructions are all exactly 16 bits (1 word) long. [[ND-100 addressing modes|Addressing mode]], [[displacement]], [[source register]], [[destination register]] are, when applicable, encoded inside the 16-bit instruction word itself. | |||
=== Memory Reference Instructions === | === Memory Reference Instructions === | ||
==== Store Instructions ==== | ==== Store Instructions ==== | ||
* [[STZ]] | * [[STZ]] – Store zero | ||
* [[STA]] | * [[STA]] – Store A | ||
* [[STT]] | * [[STT]] – Store T | ||
* [[STX]] | * [[STX]] – Store X | ||
* [[MIN]] | * [[MIN]] – Memory increase, skip if zero | ||
==== Load Instructions ==== | ==== Load Instructions ==== | ||
* [[LDA]] | * [[LDA]] – Load A | ||
* [[LDT]] | * [[LDT]] – Load T | ||
* [[LDX]] | * [[LDX]] – Load X | ||
==== Arithmetic and Logical Instructions ==== | ==== Arithmetic and Logical Instructions ==== | ||
* [[ADD]] | * [[ADD]] – Add to A (C, O and Q may also be affected) | ||
* [[SUB]] | * [[SUB]] – Subtract from A (C, O and Q may also be affected) | ||
* [[AND]] | * [[AND]] – [[Wikipedia:Logical and|Logical AND]] to A | ||
* [[ORA]] | * [[ORA]] – [[Wikipedia:inclusive or|Logical inclusive OR]] to A | ||
* [[MPY]] | * [[MPY]] – Multiply integer (O and Q may also be affected) | ||
==== Double Word Instructions ==== | ==== Double Word Instructions ==== | ||
* [[LDD]] | * [[LDD]] – Load double word | ||
* [[STD]] | * [[STD]] – Store double word | ||
==== Floating Instructions ==== | ==== Floating Instructions ==== | ||
* [[LDF]] | * [[LDF]] – Load [[floating accumulator]] | ||
* [[STF]] | * [[STF]] – Store floating accumulator | ||
* [[FAD]] | * [[FAD]] – Add to floating accumulator (TG may also be affected) | ||
* [[FSB]] | * [[FSB]] – Subtract from floating accumulator (TG may also be affected) | ||
* [[FMU]] | * [[FMU]] – Multiply floating accumulator (TG may also be affected) | ||
* [[FDV]] | * [[FDV]] – Divide floating accumulator (Z and TG may also be affected) | ||
==== Byte Instructions ==== | ==== Byte Instructions ==== | ||
* [[BFILL]] | * [[BFILL]] – Byte fill | ||
* [[MOVB]] | * [[MOVB]] – Move bytes | ||
* [[MOVBF]] | * [[MOVBF]] – Move bytes forward | ||
* [[SBYT]] | * [[SBYT]] – Store byte | ||
* [[LBYT]] | * [[LBYT]] – Load byte | ||
=== Execute Instruction === | === Execute Instruction === | ||
* [[EXR]] | * [[EXR]] – Execute instruction found in specified register | ||
=== Argument Instructions === | |||
* [[AAA]] – Add argument to A | |||
* [[AAB]] – Add argument to B | |||
* [[AAT]] – Add argument to T | |||
* [[AAX]] – Add argument to X | |||
* [[SAA]] – Set argument to A | |||
* [[SAB]] – Set argument to B | |||
* [[SAT]] – Set argument to T | |||
* [[SAX]] – Set argument to X | |||
=== Bit Instructions === | === Bit Instructions === | ||
* [[BSKP]] | * [[BSKP]] – Skip next location if specified condition is true | ||
* [[BSET]] | * [[BSET]] – Set specified bit equal to specified condition | ||
* [[BSTA]] | * [[BSTA]] – Store and clear K | ||
* [[BSTC]] | * [[BSTC]] – Store complement and set K | ||
* [[BLDA]] | * [[BLDA]] – load K | ||
* [[BLDC]] | * [[BLDC]] – Load bit complement to K | ||
* [[BANC]] | * [[BANC]] – Logical AND with bit complement | ||
* [[BORC]] | * [[BORC]] – Logical OR with bit complement | ||
* [[BAND]] | * [[BAND]] – Logical AND to K | ||
* [[BORA]] | * [[BORA]] – Logical OR to K | ||
=== Shift Instructions === | === Shift Instructions === | ||
* [[SHT]] | * [[SHT]] – Shift T register | ||
* [[SHD]] | * [[SHD]] – Shift D register | ||
* [[SHA]] | * [[SHA]] – Shift A register | ||
* [[SAD]] | * [[SAD]] – Shift A and D registers connected | ||
* | ===== Subinstructions (Types) ===== | ||
* | For each shift instruction, one of the following types can be specified | ||
* | :* ''nil (default)'' Arithmetic shift | ||
* | :* ROT – Rotational shift | ||
:* ZIN – Zero end input | |||
:* LIN – Link end input | |||
===== Subinstructions (Direction) ===== | |||
:* ''nil (default)'' Left shift | |||
:* SHR – Right shift | |||
=== System Control Instructions === | === System Control Instructions === | ||
* [[IOF]] | * [[IOF]] – Interrupt system off | ||
* [[ION]] | * [[ION]] – Interrupt system on | ||
* [[LWCS]] | * [[LWCS]] – Load Writeable Control Store | ||
* [[MON]] | * [[MON]] – Monitor Call | ||
* [[PIOF]] | * [[PIOF]] – Memory management and interrupt system off | ||
* [[PION]] | * [[PION]] – Memory management and interrupt system on | ||
* [[POF]] | * [[POF]] – Memory management off | ||
* [[PON]] | * [[PON]] – Memory management on | ||
* [[REX]] | * [[REX]] – Reset extended address mode | ||
* [[SEX]] | * [[SEX]] – Set extended address mode | ||
* [[WAIT]] | * [[WAIT]] – Wait (give up priority) | ||
* [[OPCOM]] | * [[OPCOM]] – Operator's Communication Code | ||
=== Transfer Instructions === | === Transfer Instructions === | ||
==== Load Independent Instructions ==== | ==== Load Independent Instructions ==== | ||
* [[TRA]] | * [[TRA]] – Transfer to A register | ||
* [[TRR]] | * [[TRR]] – Transfer to register | ||
==== Inter-level Instructions ==== | ==== Inter-level Instructions ==== | ||
* [[IRR]] | * [[IRR]] – Inter Register Read | ||
* [[IRW]] | * [[IRW]] – Inter Register Write | ||
=== Register Operations === | === Register Operations === | ||
==== Index register operation ==== | |||
* [[MIX3]] – Multiply index by 3 | |||
==== Arithmetic Operations, RAD=1: ==== | ==== Arithmetic Operations, RAD=1: ==== | ||
* [[RADD]] – Register addition | |||
* [[RADD]] | * [[RSUB]] – Register subtraction | ||
* [[RSUB]] | * [[COPY]] – Register transfer | ||
* [[COPY]] | ===== Subinstructions ===== | ||
* | :* AD1 – Also add 1 to destination | ||
* | :* ADC – Also add old carry to destination | ||
==== Logical Operations, RAD=0: ==== | ==== Logical Operations, RAD=0: ==== | ||
* [[SWAP]] | * [[SWAP]] – Register exchange | ||
* [[RAND]] | * [[RAND]] – Register logical AND | ||
* [[REXO]] | * [[REXO]] – Register logical exclusive OR | ||
* [[RORA]] | * [[RORA]] – Register logical OR | ||
* | ===== Subinstructions ===== | ||
* [[ | :* CLD – Clear destination register before operation | ||
:* CM1 – Use complement ([[wikipedia:ones' complement|ones' complement]]) of source register as operand. | |||
==== Combined Instructions: ==== | ==== Combined Instructions: ==== | ||
* [[EXIT]] | * [[EXIT]] – Return from subroutine | ||
* [[RCLR]] | * [[RCLR]] – Register clear | ||
* [[RINC]] | * [[RINC]] – Register increment | ||
* [[RDCR]] | * [[RDCR]] – Register decrement | ||
==== Extended Arithmetic Operations: ==== | ==== Extended Arithmetic Operations: ==== | ||
* [[RMPY]] | * [[RMPY]] – Integer inter-register multiply | ||
* [[RDIV]] | * [[RDIV]] – Integer inter-register divide | ||
=== Floating Conversion === | === Floating Conversion === | ||
* [[NLZ]] | * [[NLZ]] – Normalize (integer to floating) | ||
* [[DNZ]] | * [[DNZ]] – Denormalize (floating to integer) | ||
=== Memory Examine/Deposit Instructions === | === Memory Examine/Deposit Instructions === | ||
* [[EXAM]] | * [[EXAM]] – Memory examine | ||
* [[DEPO]] | * [[DEPO]] – Memory deposit | ||
=== Sequencing Instructions === | === Sequencing Instructions === | ||
==== Unconditional Jump ==== | ==== Unconditional Jump ==== | ||
* [[JMP]] | * [[JMP]] – Jump | ||
* [[JPL]] | * [[JPL]] – Jump to subroutine | ||
==== Conditional Jump ==== | ==== Conditional Jump ==== | ||
* [[JAP]] | * [[JAP]] – Jump if A register is positive or zero | ||
* [[JAN]] | * [[JAN]] – Jump if A register is negative | ||
* [[JAZ]] | * [[JAZ]] – Jump if A register is zero | ||
* [[JAF]] | * [[JAF]] – Jump if A register is filled (not zero) | ||
* [[JXN]] | * [[JXN]] – Jump lf X register is negative | ||
* [[ | * [[JXZ]] – Jump if X register is zero. | ||
* [[ | * [[JPC]] – Count and jump if X register is positive or zero. | ||
* [[ | * [[JNC]] – Count and jump if X register is negative. | ||
==== Skip Instructions ==== | ==== Skip Instructions ==== | ||
* [[ | * [[SKP]] – Skip next instruction if specified condition is true | ||
===== Subinstructions (Specified condition) ===== | |||
:* EQL – Equal | |||
:* GEQ – Signed greater or equal to (owerflow not OK) | |||
:* GRE – Signed greater or equal to (owerflow OK) | |||
:* MGRE – Magnitude greater or equal to | |||
:* UEQ – Unequal to | |||
:* LSS – Signed less than (owerflow not OK) | |||
:* LST – Signed less than (owerflow OK) | |||
:* MLST – Magnitude less than | |||
===== Dummys (may be used to obtain easy readability) ===== | |||
:* IF | |||
:* 0 | |||
==Additional instructions in the CE ([[Commercial extended|Commercial Extended]]) option== | |||
===Decimal Instructions=== | |||
* [[ADDD]] – Add decimal | |||
* [[SUBD]] – Subtract decimal | |||
* [[COMD]] – Compare decimal | |||
* [[SHDE]] – Decimal shift | |||
* [[PACK]] – Convert to packed decimal | |||
* [[UNPACK]] – Convert to unpacked decimal | |||
===Stack Handling Instructions=== | |||
* [[INIT]] – Initialize stack | |||
* [[ENTR]] – Enter stack | |||
* [[LEAVE]] – Leave stack | |||
* [[ELEAV]] – Error leave stack | |||
==Additional instructions in the CX option== | |||
The CX instructions include the CE instructions in improved versions, plus the following CX-only instructions: | |||
* [[MOVEW]] – Move block of words | |||
* [[TSET]] – Test and set | |||
* [[RDUS]] – Read don't use cache | |||
====SINTRAN-III Segment Change Instructions==== | |||
* [[SETPT]] – Set page tables | |||
* [[CLEPT]] – Clear page tables | |||
* [[CLNREENT]] – Clear non reentrant | |||
* [[CHREENTPAGES]] – Change not reentrant pages | |||
* [[CLEPU]] – Clear page tables, collect PGU information | |||
==New SINTRAN instructions in ND-110== | |||
* [[CLPT]] Clear segment from page tables | |||
* [[CNREK]] Clear non re-entrant pages | |||
* [[ENPT]] Enter segment in page tables | |||
* [[INSPL]] Insert page in page list | |||
* [[REMPL]] Remove page from page list | |||
* [[REPT]] Enter re-entrant segment in page tables | |||
== Undocumented instructions == | |||
* [[GECO]] | |||
* [[IOT]] | |||
== Sources == | == Sources == | ||
*{{ND-doc|06.014|(ND-06.014.02 rev A)}} | *{{ND-doc|06.014|(ND-06.014.02 rev A)}} | ||
*ND- | *{{ND-doc|06.029|(ND-06.029.01 rev A)}} | ||
*{{ND-doc|99.005|(ND-99.005.02 12/84)}} | |||
[[Category:ND-100 instructions|*]] |
Latest revision as of 13:25, 8 February 2012
See also: ND-1xx Instructions Sorted Numerically
Instruction Set
NORD-10/ND-100/ND-120 instructions are all exactly 16 bits (1 word) long. Addressing mode, displacement, source register, destination register are, when applicable, encoded inside the 16-bit instruction word itself.
Memory Reference Instructions
Store Instructions
Load Instructions
Arithmetic and Logical Instructions
- ADD – Add to A (C, O and Q may also be affected)
- SUB – Subtract from A (C, O and Q may also be affected)
- AND – Logical AND to A
- ORA – Logical inclusive OR to A
- MPY – Multiply integer (O and Q may also be affected)
Double Word Instructions
Floating Instructions
- LDF – Load floating accumulator
- STF – Store floating accumulator
- FAD – Add to floating accumulator (TG may also be affected)
- FSB – Subtract from floating accumulator (TG may also be affected)
- FMU – Multiply floating accumulator (TG may also be affected)
- FDV – Divide floating accumulator (Z and TG may also be affected)
Byte Instructions
Execute Instruction
- EXR – Execute instruction found in specified register
Argument Instructions
- AAA – Add argument to A
- AAB – Add argument to B
- AAT – Add argument to T
- AAX – Add argument to X
- SAA – Set argument to A
- SAB – Set argument to B
- SAT – Set argument to T
- SAX – Set argument to X
Bit Instructions
- BSKP – Skip next location if specified condition is true
- BSET – Set specified bit equal to specified condition
- BSTA – Store and clear K
- BSTC – Store complement and set K
- BLDA – load K
- BLDC – Load bit complement to K
- BANC – Logical AND with bit complement
- BORC – Logical OR with bit complement
- BAND – Logical AND to K
- BORA – Logical OR to K
Shift Instructions
- SHT – Shift T register
- SHD – Shift D register
- SHA – Shift A register
- SAD – Shift A and D registers connected
Subinstructions (Types)
For each shift instruction, one of the following types can be specified
- nil (default) Arithmetic shift
- ROT – Rotational shift
- ZIN – Zero end input
- LIN – Link end input
Subinstructions (Direction)
- nil (default) Left shift
- SHR – Right shift
System Control Instructions
- IOF – Interrupt system off
- ION – Interrupt system on
- LWCS – Load Writeable Control Store
- MON – Monitor Call
- PIOF – Memory management and interrupt system off
- PION – Memory management and interrupt system on
- POF – Memory management off
- PON – Memory management on
- REX – Reset extended address mode
- SEX – Set extended address mode
- WAIT – Wait (give up priority)
- OPCOM – Operator's Communication Code
Transfer Instructions
Load Independent Instructions
Inter-level Instructions
Register Operations
Index register operation
- MIX3 – Multiply index by 3
Arithmetic Operations, RAD=1:
Subinstructions
- AD1 – Also add 1 to destination
- ADC – Also add old carry to destination
Logical Operations, RAD=0:
- SWAP – Register exchange
- RAND – Register logical AND
- REXO – Register logical exclusive OR
- RORA – Register logical OR
Subinstructions
- CLD – Clear destination register before operation
- CM1 – Use complement (ones' complement) of source register as operand.
Combined Instructions:
- EXIT – Return from subroutine
- RCLR – Register clear
- RINC – Register increment
- RDCR – Register decrement
Extended Arithmetic Operations:
Floating Conversion
Memory Examine/Deposit Instructions
Sequencing Instructions
Unconditional Jump
Conditional Jump
- JAP – Jump if A register is positive or zero
- JAN – Jump if A register is negative
- JAZ – Jump if A register is zero
- JAF – Jump if A register is filled (not zero)
- JXN – Jump lf X register is negative
- JXZ – Jump if X register is zero.
- JPC – Count and jump if X register is positive or zero.
- JNC – Count and jump if X register is negative.
Skip Instructions
- SKP – Skip next instruction if specified condition is true
Subinstructions (Specified condition)
- EQL – Equal
- GEQ – Signed greater or equal to (owerflow not OK)
- GRE – Signed greater or equal to (owerflow OK)
- MGRE – Magnitude greater or equal to
- UEQ – Unequal to
- LSS – Signed less than (owerflow not OK)
- LST – Signed less than (owerflow OK)
- MLST – Magnitude less than
Dummys (may be used to obtain easy readability)
- IF
- 0
Additional instructions in the CE (Commercial Extended) option
Decimal Instructions
- ADDD – Add decimal
- SUBD – Subtract decimal
- COMD – Compare decimal
- SHDE – Decimal shift
- PACK – Convert to packed decimal
- UNPACK – Convert to unpacked decimal
Stack Handling Instructions
Additional instructions in the CX option
The CX instructions include the CE instructions in improved versions, plus the following CX-only instructions:
SINTRAN-III Segment Change Instructions
- SETPT – Set page tables
- CLEPT – Clear page tables
- CLNREENT – Clear non reentrant
- CHREENTPAGES – Change not reentrant pages
- CLEPU – Clear page tables, collect PGU information
New SINTRAN instructions in ND-110
- CLPT Clear segment from page tables
- CNREK Clear non re-entrant pages
- ENPT Enter segment in page tables
- INSPL Insert page in page list
- REMPL Remove page from page list
- REPT Enter re-entrant segment in page tables
Undocumented instructions
Sources
- Norsk Data Document ND–06.014 ND-100 REFERENCE MANUAL (ND-06.014.02 rev A)
- Norsk Data Document ND–06.029 ND-110 Instruction Set (ND-06.029.01 rev A)
- Norsk Data Document ND–99.005 ND-100 INSTANT INSTRUCTION CODES (ND-99.005.02 12/84)