Master Clear: Difference between revisions
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== Master clear routine == | == Master clear routine == | ||
The master clear routine turns off running indicator, the [[PIE]] | The master clear routine turns off running indicator, the [[PIE register]] is cleared. The paging and interrupt systems are turned off. | ||
The paging system is set in "normal" mode (as if the [[REX]] instruction had been executed). | The paging system is set in "normal" mode (as if the [[REX]] instruction had been executed). | ||
The CPU self-test routine microprogram is executed. If no errors are found, the running indicator lamp is lit, and the terminal interface on the CPU board (terminal no. 1) is initialized to 7-bit plus even parity. Parity is not checked on input. | The CPU self-test routine microprogram is executed. If no errors are found, the running indicator lamp is lit, and the terminal interface on the CPU board (terminal no. 1) is initialized to 7-bit plus even parity. Parity is not checked on input. | ||
When the master clear routine is finished, the CPU will be in STOP mode. | When the master clear routine is finished, the CPU will be in STOP mode. | ||
== References == | == References == | ||
* {{ND-doc|06.026.1|Chapter 7 Operator Interaction}} | * {{ND-doc|06.026.1|Chapter 7 Operator Interaction}} | ||
Revision as of 23:12, 20 December 2011
The MCL (Master Clear) button is used to force the computer into a defined initial state. The CPU loads the microprogram into the control store from the EPROM where it is stored. The microprogram then traps to the master clear routine. This initialization is also performed when the CPU goes through the power up sequence, and when the bus line (negative logic) BMCL is activated.
Master clear routine
The master clear routine turns off running indicator, the PIE register is cleared. The paging and interrupt systems are turned off. The paging system is set in "normal" mode (as if the REX instruction had been executed). The CPU self-test routine microprogram is executed. If no errors are found, the running indicator lamp is lit, and the terminal interface on the CPU board (terminal no. 1) is initialized to 7-bit plus even parity. Parity is not checked on input.
When the master clear routine is finished, the CPU will be in STOP mode.
References
- Norsk Data Document ND–06.026.1 ND-110 Functional Description Chapter 7 Operator Interaction