ND-1xx Instructions - Revision history

TArntsen: There is a 'Commercial Extended' page now, link to it.

2012-02-08T13:25:12Z

There is a 'Commercial Extended' page now, link to it.

← Older revision		Revision as of 13:25, 8 February 2012
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	:* 0		:* 0

	==Additional instructions in the CE (Commercial Extended) option==		==Additional instructions in the CE ([[Commercial extended\|Commercial Extended]]) option==
	===Decimal Instructions===		===Decimal Instructions===
	* [[ADDD]] – Add decimal		* [[ADDD]] – Add decimal

TArntsen: Added reference to sorted list

2011-05-16T15:02:56Z

Added reference to sorted list

← Older revision		Revision as of 15:02, 16 May 2011
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			See also: [[ND-1xx Instructions Sorted Numerically]]

	== Instruction Set ==		== Instruction Set ==
	NORD-10/ND-100/ND-120 instructions are all exactly 16 bits (1 word) long. [[ND-100 addressing modes\|Addressing mode]], [[displacement]], [[source register]], [[destination register]] are, when applicable, encoded inside the 16-bit instruction word itself.		NORD-10/ND-100/ND-120 instructions are all exactly 16 bits (1 word) long. [[ND-100 addressing modes\|Addressing mode]], [[displacement]], [[source register]], [[destination register]] are, when applicable, encoded inside the 16-bit instruction word itself.

TArntsen: Undocumented instructions: Add GECO

2011-05-15T10:31:03Z

Undocumented instructions: Add GECO

← Older revision		Revision as of 10:31, 15 May 2011
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	== Undocumented instructions ==		== Undocumented instructions ==
			* [[GECO]]
	* [[IOT]]		* [[IOT]]

TArntsen: Section for undocumented instruction(s)

2010-08-03T09:57:56Z

Section for undocumented instruction(s)

← Older revision		Revision as of 09:57, 3 August 2010
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	* [[REMPL]] Remove page from page list		* [[REMPL]] Remove page from page list
	* [[REPT]] Enter re-entrant segment in page tables		* [[REPT]] Enter re-entrant segment in page tables

			== Undocumented instructions ==
			* [[IOT]]

	== Sources ==		== Sources ==

TArntsen: For FAD/FSB/FMU/FDV TG (rounding indicator bit) may be affected, not C

2010-07-01T09:16:13Z

For FAD/FSB/FMU/FDV TG (rounding indicator bit) may be affected, not C

← Older revision		Revision as of 09:16, 1 July 2010
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	* [[LDF]] – Load [[floating accumulator]]		* [[LDF]] – Load [[floating accumulator]]
	* [[STF]] – Store floating accumulator		* [[STF]] – Store floating accumulator
	* [[FAD]] – Add to floating accumulator (C may also be affected)		* [[FAD]] – Add to floating accumulator (TG may also be affected)
	* [[FSB]] – Subtract from floating accumulator (C may also be affected)		* [[FSB]] – Subtract from floating accumulator (TG may also be affected)
	* [[FMU]] – Multiply floating accumulator (C may also be affected)		* [[FMU]] – Multiply floating accumulator (TG may also be affected)
	* [[FDV]] – Divide floating accumulator (Z and C may also be affected)		* [[FDV]] – Divide floating accumulator (Z and TG may also be affected)

	==== Byte Instructions ====		==== Byte Instructions ====

TArntsen: MIX3 listed

2009-10-06T15:56:16Z

MIX3 listed

← Older revision		Revision as of 15:56, 6 October 2009
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	=== Register Operations ===		=== Register Operations ===
			==== Index register operation ====
			* [[MIX3]] – Multiply index by 3

	==== Arithmetic Operations, RAD=1: ====		==== Arithmetic Operations, RAD=1: ====
	* [[RADD]] – Register addition		* [[RADD]] – Register addition

TArntsen: Fixed typo: Duplicate 'from'.

2009-08-17T12:13:22Z

Fixed typo: Duplicate 'from'.

← Older revision		Revision as of 12:13, 17 August 2009
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	==New SINTRAN instructions in ND-110==		==New SINTRAN instructions in ND-110==
	* [[CLPT]] Clear segment ~~from~~ from page tables		* [[CLPT]] Clear segment from page tables
	* [[CNREK]] Clear non re-entrant pages		* [[CNREK]] Clear non re-entrant pages
	* [[ENPT]] Enter segment in page tables		* [[ENPT]] Enter segment in page tables

TArntsen: Small instruction intro.

2009-08-13T14:27:01Z

Small instruction intro.

← Older revision		Revision as of 14:27, 13 August 2009
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	== Instruction Set ==		== Instruction Set ==
			NORD-10/ND-100/ND-120 instructions are all exactly 16 bits (1 word) long. [[ND-100 addressing modes\|Addressing mode]], [[displacement]], [[source register]], [[destination register]] are, when applicable, encoded inside the 16-bit instruction word itself.

	=== Memory Reference Instructions ===		=== Memory Reference Instructions ===
	==== Store Instructions ====		==== Store Instructions ====

Mike: Removing links for "Subinstructions", since they should not be articles

2009-08-09T19:33:16Z

Removing links for "Subinstructions", since they should not be articles

← Older revision		Revision as of 19:33, 9 August 2009
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	For each shift instruction, one of the following types can be specified		For each shift instruction, one of the following types can be specified
	:* ''nil (default)'' Arithmetic shift		:* ''nil (default)'' Arithmetic shift
	:* [[ROT]] – Rotational shift		:* ROT – Rotational shift
	:* [[ZIN]] – Zero end input		:* ZIN – Zero end input
	:* [[LIN]] – Link end input		:* LIN – Link end input
	===== Subinstructions (Direction) =====		===== Subinstructions (Direction) =====
	:* ''nil (default)'' Left shift		:* ''nil (default)'' Left shift
	:* [[SHR]] – Right shift		:* SHR – Right shift

	=== System Control Instructions ===		=== System Control Instructions ===
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	* [[RSUB]] – Register subtraction		* [[RSUB]] – Register subtraction
	* [[COPY]] – Register transfer		* [[COPY]] – Register transfer
	===== ~~Subinstruction~~ =====		===== Subinstructions =====
	:* [[AD1]] – Also add 1 to destination		:* AD1 – Also add 1 to destination
	:* [[ADC]] – Also add old carry to destination		:* ADC – Also add old carry to destination

	==== Logical Operations, RAD=0: ====		==== Logical Operations, RAD=0: ====
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	* [[REXO]] – Register logical exclusive OR		* [[REXO]] – Register logical exclusive OR
	* [[RORA]] – Register logical OR		* [[RORA]] – Register logical OR
	===== ~~Subinstruction~~ =====		===== Subinstructions =====
	:* [[CLD]] – Clear destination register before operation		:* CLD – Clear destination register before operation
	:* [[CM1]] – Use complement ([[wikipedia:ones' complement\|ones' complement]]) of source register as operand.		:* CM1 – Use complement ([[wikipedia:ones' complement\|ones' complement]]) of source register as operand.

	==== Combined Instructions: ====		==== Combined Instructions: ====
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	* [[SKP]] – Skip next instruction if specified condition is true		* [[SKP]] – Skip next instruction if specified condition is true
	===== Subinstructions (Specified condition) =====		===== Subinstructions (Specified condition) =====
	:* [[EQL]] – Equal		:* EQL – Equal
	:* [[GEQ]] – Signed greater or equal to (owerflow not OK)		:* GEQ – Signed greater or equal to (owerflow not OK)
	:* [[GRE]] – Signed greater or equal to (owerflow OK)		:* GRE – Signed greater or equal to (owerflow OK)
	:* [[MGRE]] – Magnitude greater or equal to		:* MGRE – Magnitude greater or equal to
	:* [[UEQ]] – Unequal to		:* UEQ – Unequal to
	:* [[LSS]] – Signed less than (owerflow not OK)		:* LSS – Signed less than (owerflow not OK)
	:* [[LST]] – Signed less than (owerflow OK)		:* LST – Signed less than (owerflow OK)
	:* [[MLST]] – Magnitude less than		:* MLST – Magnitude less than
	===== Dummys (may be used to obtain easy readability) =====		===== Dummys (may be used to obtain easy readability) =====
	:* IF		:* IF

TArntsen: List argument instructins

2009-08-08T13:37:42Z

List argument instructins

@@ Line 41: / Line 41: @@
 === Execute Instruction ===
 * [[EXR]] &ndash; Execute instruction found in specified register
 === Bit Instructions ===