ND-100 - Revision history

Tingo: add it to the category ND-100 hardware

2023-12-26T14:31:11Z

add it to the category ND-100 hardware

← Older revision		Revision as of 14:31, 26 December 2023
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	*{{OriginWP-EN\|NORD-100\|4th August 2008}}		*{{OriginWP-EN\|NORD-100\|4th August 2008}}
	*{{ND-doc\|06.014.02}}		*{{ND-doc\|06.014.02}}

			[[Category:ND-100 hardware]]

RHansen: /* CPU */ Minor facts added to ND-120/CX

2023-12-22T03:55:08Z

CPU: Minor facts added to ND-120/CX

← Older revision		Revision as of 03:55, 22 December 2023
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	*ND-110, incrementally improved ND-100. Same performance and instruction set as the ND-100/CX.		*ND-110, incrementally improved ND-100. Same performance and instruction set as the ND-100/CX.
	*ND-110/CX, a faster version of the ND-110 (1.5-3.5 times faster).		*ND-110/CX, a faster version of the ND-110 (1.5-3.5 times faster).
	*ND-120/CX, completely redesigned.		*ND-120/CX, completely redesigned using one big VLSI gate array (The so-called Delilah chip). Performance is approximate 1.9 times faster than the ND-110/CX. Minor changes in the microcode, no changes in the macrocode/opcodes.
	*ND-125/CX, a 120 CPU board with faster access to onboard memory and increased onboard memory size.		*ND-125/CX, a 120 CPU board with faster access to onboard memory and increased onboard memory size.

Tingo: /* ND-125/CX */ add text to the reference link

2022-10-05T17:33:36Z

ND-125/CX: add text to the reference link

← Older revision		Revision as of 17:33, 5 October 2022
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	===ND-125/CX===		===ND-125/CX===
	The ND-125 CPU appears to be based on an ND-120 CPU, but with improved performance by speeding up memory access to the on-board memory, and by increasing the on-board memory size to 8, 12, or 16 megabytes (the ND-120/CX could have a maximum of 6MB on-board). The larger memory size is achieved by using 4-Mbyte SIMMs instead of 1-Mbyte SIPs. Memory cycle time is reduced to 150 ns by using 70 ns memory modules instead of 100 ns modules.<ref>[http://sintran.com/sintran/library/libeco/ECO-ND-100-786.pdf]</ref>		The ND-125 CPU appears to be based on an ND-120 CPU, but with improved performance by speeding up memory access to the on-board memory, and by increasing the on-board memory size to 8, 12, or 16 megabytes (the ND-120/CX could have a maximum of 6MB on-board). The larger memory size is achieved by using 4-Mbyte SIMMs instead of 1-Mbyte SIPs. Memory cycle time is reduced to 150 ns by using 70 ns memory modules instead of 100 ns modules.<ref>[http://sintran.com/sintran/library/libeco/ECO-ND-100-786.pdf sintran.com, ECO 100-786, date: 1994.09.09]</ref>

	==Surviving systems==		==Surviving systems==

TArntsen: ND-125/CX - some more details

2022-10-05T14:47:25Z

ND-125/CX - some more details

← Older revision		Revision as of 14:47, 5 October 2022
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	===ND-125/CX===		===ND-125/CX===
	The ND-125 CPU appears to be based on an ND-120 CPU, but with improved performance by speeding up memory access to the on-board memory, and by increasing the on-board memory size to 8, 12, or 16 megabytes (the ND-120/CX could have a maximum of 6MB on-board).<ref>[http://sintran.com/sintran/library/libeco/ECO-ND-100-786.pdf]</ref>		The ND-125 CPU appears to be based on an ND-120 CPU, but with improved performance by speeding up memory access to the on-board memory, and by increasing the on-board memory size to 8, 12, or 16 megabytes (the ND-120/CX could have a maximum of 6MB on-board). The larger memory size is achieved by using 4-Mbyte SIMMs instead of 1-Mbyte SIPs. Memory cycle time is reduced to 150 ns by using 70 ns memory modules instead of 100 ns modules.<ref>[http://sintran.com/sintran/library/libeco/ECO-ND-100-786.pdf]</ref>

	==Surviving systems==		==Surviving systems==

TArntsen: CPU: Add 125/CX to introduction list

2020-01-15T07:56:26Z

CPU: Add 125/CX to introduction list

← Older revision		Revision as of 07:56, 15 January 2020
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	*ND-110/CX, a faster version of the ND-110 (1.5-3.5 times faster).		*ND-110/CX, a faster version of the ND-110 (1.5-3.5 times faster).
	*ND-120/CX, completely redesigned.		*ND-120/CX, completely redesigned.
			*ND-125/CX, a 120 CPU board with faster access to onboard memory and increased onboard memory size.

	The ND-100 line was machine-instruction compatible with the Nord-10 line, except for some "extended instructions", all in supervisor mode, mostly used by the operating system. Like most processors of its time, the native bit grouping was octal, despite the 16-bit word length.		The ND-100 line was machine-instruction compatible with the Nord-10 line, except for some "extended instructions", all in supervisor mode, mostly used by the operating system. Like most processors of its time, the native bit grouping was octal, despite the 16-bit word length.

TArntsen: Removed a

2020-01-10T14:26:56Z

Removed a

← Older revision		Revision as of 14:26, 10 January 2020
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	{\| style="width:100%;" border="1"		{\| style="width:100%;" border="1"
	\|+ Relative CPU performance		\|+ Relative CPU performance
	! !! ND-100 !! ND-100/CE !! ND-110 !! ND-110/CX !! ND-120/CX !! ND-125/CX~~{{Citation_needed}}~~		! !! ND-100 !! ND-100/CE !! ND-110 !! ND-110/CX !! ND-120/CX !! ND-125/CX
	\|-		\|-
	\| Minimum number of microinstructions per instruction \|\| 3 \|\| 3 \|\| 1 \|\| 1		\| Minimum number of microinstructions per instruction \|\| 3 \|\| 3 \|\| 1 \|\| 1 \|\| \|\|
	\|-		\|-
	\| Minimum microinstruction cycle time \|\| 150ns \|\| 150ns \|\| 100ns \|\| 100ns		\| Minimum microinstruction cycle time \|\| 150ns \|\| 150ns \|\| 100ns \|\| 100ns \|\| \|\|
	\|}		\|}

TArntsen: ND-125/CX

2020-01-10T14:25:59Z

ND-125/CX

← Older revision		Revision as of 14:25, 10 January 2020
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	The Samson/Delilah naming scheme may reflect that around the time of the development of the ND-120, it was increasingly clear that the mixed 16/32-bit architecture was a bottleneck for the ND-500(0) architecture; Internal technical documentation used at Norsk Data for the Delilah chip has a drawing of a grinning woman with hair in her clenched fist.		The Samson/Delilah naming scheme may reflect that around the time of the development of the ND-120, it was increasingly clear that the mixed 16/32-bit architecture was a bottleneck for the ND-500(0) architecture; Internal technical documentation used at Norsk Data for the Delilah chip has a drawing of a grinning woman with hair in her clenched fist.

			===ND-125/CX===
			The ND-125 CPU appears to be based on an ND-120 CPU, but with improved performance by speeding up memory access to the on-board memory, and by increasing the on-board memory size to 8, 12, or 16 megabytes (the ND-120/CX could have a maximum of 6MB on-board).<ref>[http://sintran.com/sintran/library/libeco/ECO-ND-100-786.pdf]</ref>

	==Surviving systems==		==Surviving systems==

Gandalf: Added a note about the ND-110PCX BUTTERFLY 110 CPU.

2018-12-30T19:13:16Z

Added a note about the ND-110PCX BUTTERFLY 110 CPU.

← Older revision		Revision as of 19:13, 30 December 2018
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	===ND-110/CX===		===ND-110/CX===
	This is the fast version of the [[ND-110 CPU]].		This is the fast version of the [[ND-110 CPU]], also known as '''RASK'''.

			===ND-110PCX===
			This is the CPU used in the [[BUTTERFLY 110]] PC-based workstation. The CPU is implemented on two full length ISA cards and based on the same design as ND-110/CX.

	===ND-120/CX===		===ND-120/CX===

Gandalf: Added a section for surviving systems.

2016-08-19T08:51:10Z

Added a section for surviving systems.

← Older revision		Revision as of 08:51, 19 August 2016
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	The Samson/Delilah naming scheme may reflect that around the time of the development of the ND-120, it was increasingly clear that the mixed 16/32-bit architecture was a bottleneck for the ND-500(0) architecture; Internal technical documentation used at Norsk Data for the Delilah chip has a drawing of a grinning woman with hair in her clenched fist.		The Samson/Delilah naming scheme may reflect that around the time of the development of the ND-120, it was increasingly clear that the mixed 16/32-bit architecture was a bottleneck for the ND-500(0) architecture; Internal technical documentation used at Norsk Data for the Delilah chip has a drawing of a grinning woman with hair in her clenched fist.

			==Surviving systems==
			There are quite a lot of surviving ND-100 systems remaining. This list is far from complete.
			* ND-100 serial 383 : In the collections of Telemuseet<ref>[http://digitaltmuseum.no/021026130703 Collections of Telemuseet, TELE.Hf-226]</ref>

	==Gallery==		==Gallery==
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	*[[Wikipedia:NORD-100]]		*[[Wikipedia:NORD-100]]

	== ~~Sources~~ ==		== References ==
			<references/>
	*{{OriginWP-EN\|NORD-100\|4th August 2008}}		*{{OriginWP-EN\|NORD-100\|4th August 2008}}
	*{{ND-doc\|06.014.02}}		*{{ND-doc\|06.014.02}}

TArntsen: Updated the shortlist about ND-110+ND-110/CX based on the talk page, references, and the ND-110 CPU article.

2016-05-23T05:43:38Z

Updated the shortlist about ND-110+ND-110/CX based on the talk page, references, and the ND-110 CPU article.

← Older revision		Revision as of 05:43, 23 May 2016
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	*NORD-100/CE, Commercial Extended, with decimal arithmetic instructions		*NORD-100/CE, Commercial Extended, with decimal arithmetic instructions
	*ND-100/CX, improved the CE instructions and added some new instructions		*ND-100/CX, improved the CE instructions and added some new instructions
	*ND-110, incrementally improved ND-100		*ND-110, incrementally improved ND-100. Same performance and instruction set as the ND-100/CX.
	*ND-110/CX, a faster ND-110 ~~cpu~~.		*ND-110/CX, a faster version of the ND-110 (1.5-3.5 times faster).
	*ND-120/CX, completely redesigned.		*ND-120/CX, completely redesigned.