LWCS - Revision history

TArntsen: Spellfix: Arcitecture -> Architecture

2009-08-03T13:34:43Z

Spellfix: Arcitecture -> Architecture

← Older revision		Revision as of 13:34, 3 August 2009
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	\|Affected=		\|Affected=
	\|Type=Privileged		\|Type=Privileged
	\|~~Arcitecture~~=[[NORD-10]], [[ND-100]] ([[ND-110 CPU\|ND-110]])		\|Architecture=[[NORD-10]], [[ND-100]] ([[ND-110 CPU\|ND-110]])
	}}		}}

	'''LWCS''' is an instruction on the ND platform. It ~~load~~ the contents of [[main memory]] locations with addresses from 15K to 16K into the optional 256 word by 64 bit RAM writeable [[control store]].		'''LWCS''' is an instruction on the ND platform. It loads the contents of [[main memory]] locations with addresses from 15K to 16K into the optional 256 word by 64 bit RAM writeable [[control store]].

	Microprogram addresses from 7400<sub><small>8</small></sub> to 7777<sub><small>8</small></sub> will then be accessible. When the instruction is finished, all microprogram addresses are legal and illegal instruct. [[ROM out of range interrupt]] will never occur.		Microprogram addresses from 7400<sub><small>8</small></sub> to 7777<sub><small>8</small></sub> will then be accessible. When the instruction is finished, all microprogram addresses are legal and illegal instruct. [[ROM out of range interrupt]] will never occur.

Gandalf: Added note about ND-110

2009-04-05T10:54:18Z

Added note about ND-110

← Older revision		Revision as of 10:54, 5 April 2009
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	== No-operation ==		== No-operation ==
	LWCS is a [[no-operation]] in the ND-110. The ND-110 is software compatible but not microcode compatible and writing to the writable control store has no meaning in the ND-110. A no-operation is executed so that programs written for the ND-100 and NORD-10 can continue.		LWCS is a [[no-operation]] in the ND-110. The ND-110 is software compatible but not microcode compatible and writing to the writable control store has no meaning in the ND-110. A no-operation is executed so that programs written for the ND-100 and NORD-10 can continue.

			For the ND-110 series of CPUs see instructions [[TRA]] CS and [[TRR]] CS for access to the control store.

	== References ==		== References ==

Mike: Adopt to new format in template

2009-04-03T18:39:47Z

Adopt to new format in template

← Older revision		Revision as of 18:39, 3 April 2009
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	\|Description=Load Writeable Control Store		\|Description=Load Writeable Control Store
	\|Format=LWCS		\|Format=LWCS
	\|Code=143 500~~<sub><small>8</small></sub>~~		\|Code=143 500
	\|Affected=		\|Affected=
	\|Privileged~~=Yes~~		\|Type=Privileged
	\|Arcitecture=[[NORD-10]], [[ND-100]] ([[ND-110 CPU\|ND-110]])		\|Arcitecture=[[NORD-10]], [[ND-100]] ([[ND-110 CPU\|ND-110]])
	}}		}}

	'''LWCS''' is an instruction on the ND platform. It load the contents of [[main memory]] locations with addresses from 15K to 16K into the optional 256 word by 64 bit RAM writeable control store.		'''LWCS''' is an instruction on the ND platform. It load the contents of [[main memory]] locations with addresses from 15K to 16K into the optional 256 word by 64 bit RAM writeable [[control store]].

	Microprogram addresses from 7400<sub><small>8</small></sub> to 7777<sub><small>8</small></sub> will then be accessible. When the instruction is finished, all microprogram addresses are legal and illegal instruct. [[ROM out of range interrupt]] will never occur.		Microprogram addresses from 7400<sub><small>8</small></sub> to 7777<sub><small>8</small></sub> will then be accessible. When the instruction is finished, all microprogram addresses are legal and illegal instruct. [[ROM out of range interrupt]] will never occur.

Mike: New page: {{InstructionBox |Mnemonic=LWCS |Description=Load Writeable Control Store |Format=LWCS |Code=143 500₈ |Affected= |Privileged=Yes |Arcitecture=NORD-10, [[...

2009-04-02T16:15:43Z

New page: {{InstructionBox |Mnemonic=LWCS |Description=Load Writeable Control Store |Format=LWCS |Code=143 5008 |Affected= |Privileged=Yes |Arcitecture=NORD-10, [[...

New page

{{InstructionBox
|Mnemonic=LWCS
|Description=Load Writeable Control Store
|Format=LWCS
|Code=143 5008
|Affected=
|Privileged=Yes
|Arcitecture=[[NORD-10]], [[ND-100]] ([[ND-110 CPU|ND-110]])
}}

'''LWCS''' is an instruction on the ND platform. It load the contents of [[main memory]] locations with addresses from 15K to 16K into the optional 256 word by 64 bit RAM writeable control store.

Microprogram addresses from 74008 to 77778 will then be accessible. When the instruction is finished, all microprogram addresses are legal and illegal instruct. [[ROM out of range interrupt]] will never occur.

The LWCS-instruction must always be performed before executing instructions using microaddresses in the range 4000-7777. This is necessary even if no writeable control store option is installed. The microinstructions from 4000 to 7777 are only used by instructions described in the chapters on the CE or CX options.

== No-operation ==
LWCS is a [[no-operation]] in the ND-110. The ND-110 is software compatible but not microcode compatible and writing to the writable control store has no meaning in the ND-110. A no-operation is executed so that programs written for the ND-100 and NORD-10 can continue.

== References ==
*{{ND-doc|06.014.02|Page 186}}
*{{ND-doc|06.029.01|Page 131}}

[[Category:ND-100 instructions]]

LWCS - Revision history

TArntsen: Spellfix: Arcitecture -> Architecture

Gandalf: Added note about ND-110

Mike: Adopt to new format in template

Mike: New page: {{InstructionBox |Mnemonic=LWCS |Description=Load Writeable Control Store |Format=LWCS |Code=143 5008 |Affected= |Privileged=Yes |Arcitecture=NORD-10, [[...

Mike: New page: {{InstructionBox |Mnemonic=LWCS |Description=Load Writeable Control Store |Format=LWCS |Code=143 500₈ |Affected= |Privileged=Yes |Arcitecture=NORD-10, [[...