View source for FDV

{{InstructionBox
|Mnemonic=FDV
|Description=Divide floating accumulator
|Format=FDV ''<[[ND-100 addressing modes|addr. mode]]> <[[displacement|disp.]]>''
|Code=114&nbsp;000
|Affected=T A D, Z, TG
|Architecture=[[ND-100]], [[ND-110 CPU|ND-110]]
}}

'''FDV''' is an assembly instruction. The contents of the [[floating accumulator]] is divided by the floating word in the [[effective address]] and the following one or two locations, with the result in the floating accumulator (T A D).

If division by zero is attempted the error indicator '''Z''' is set to one.

On 32-bit floating point hardware only registers '''A''' and '''D''' are used, and two address locations instead of three (ea and ea+1).

== Flags affected ==
The [[rounding indicator]] for floating point operations ('''TG''', sometimes called just '''G''') may be set by this instruction.<br>
The [[error indicator]] ('''Z''') is set if division by zero is attempted. The flag may be tested by a following [[BSKP]] instruction.

== References ==
*{{ND-doc|06.014.02|Page 3-23}}
*{{ND-doc|06.029.01|Pages 69 and 72}}
[[Category:ND-100 instructions]]