ND-100 Satellite 14.16796: Difference between revisions
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|+ Hardware Components | |+ Hardware Components | ||
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! Slot!! Part Number !! PCB Number !! Description !! Print Version !! ECO | ! Slot!! Part Number !! PCB Number !! Description !! Print Version !! ECO | ||
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== History == | == History == | ||
: 2024-10-03: Trying to identify signals from the HDLC output connector using a scope to find clock signal, but was rather unsuccessful.. maybe I am not expected to see clean digital clock signals - all I could find was somewhat analog. I really need to find some description for where where TX +/- and send clock +/- is supposed to be on the connectors. | |||
: 2024-10-03: Tried to get ASYNC terminals to work. Unable to find any way to do loopback test with valid results. I might need to re-configure to RS-232 as it may be Current-Loop. Maybe card is defect? | |||
: 2024-10-03: Booted SINTRAN from the MFM HDD emulator. Managed to get MegaLink card to work with XMSG subsystem, but I first had to reconfigure the device address so it became MegaLink #1 (was #5 in the other machine) | |||
: 2024-10-03: There was one free slot in the machine, marked HDLC. Moved over a MegaLink card from my other machine, and now I could boot from floppy. Ran test programs and things seeem ok. Still some strange results in CONFIGURE first time I run it. | |||
: 2024-10-03: Tried to boot from floppy, but system just hung. Seemed like INTERRUPT or IDENT signals somehow got lost. | |||
: 2024-10-03: Opened the keylock and managed to get power to the system. Inserted back all the cards, one by one, and no smoke signals. Got console access. | |||
: 2024-08-18: Tried to image the MFM HDD, but failed - disk unreadable | : 2024-08-18: Tried to image the MFM HDD, but failed - disk unreadable | ||
: 2024-08-18: Started going through the system, documenting it and basic cleaning in preparation for getting it up. | : 2024-08-18: Started going through the system, documenting it and basic cleaning in preparation for getting it up. | ||
: 2024-08-17: System donated to me from Håvard Sten | : 2024-08-17: System donated to me from Håvard Sten | ||
== TEST PROGRAMS == | |||
=== OUTPUT FROM TEST PROGRAM 'CONFIGURE' === | |||
<div class="mw-code"><pre> | |||
CONFIGURATION - Version: D05 - 1988-11-08 | |||
> RUN | |||
H A R D W A R E C O N F I G U R A T I O N | |||
============================================= | |||
CPU type.............: ND-100/CX upgraded for 16 PITs | |||
Floating format......: 48 bits | |||
Memory management....: MMS-2 | |||
Cache................: Manually disabled | |||
ALD register content.: 20500B | |||
Total memory size....: 2.000 Mbytes | |||
FIRST LAST I D E N T C O D E S LOG. | |||
HARDWARE DEVICE NAME DEVNO DEVNO LEV10 LEV11 LEV12 LEV13 DEVNO | |||
------------------------------------------------------------------------------- | |||
REAL TIME CLOCK 1 10 13 1 | |||
TERMINAL INTERFACE 1 300 307 == Identcode not checked == 1 | |||
TERMINAL INTERFACE 5 340 347 44 44 44 | |||
TERMINAL INTERFACE 6 350 357 45 45 45 | |||
TERMINAL INTERFACE 7 360 367 46 46 46 | |||
TERMINAL INTERFACE 8 370 377 47 47 47 | |||
ST506 5" DISC CONTR. 1 500 507 1 1224 | |||
TERMINAL INTERFACE 9 1300 1307 50 50 60 | |||
TERMINAL INTERFACE 10 1310 1317 51 51 61 | |||
TERMINAL INTERFACE 11 1320 1327 52 52 62 | |||
TERMINAL INTERFACE 12 1330 1337 53 53 63 | |||
FLOPPY & STREAMER 5 & 8 1 1560 1567 21 1145 | |||
HDLC REMOTE LOAD 1 1604 1607 | |||
HDLC / MEGALINK 5 1740 1757 154 154 1370 | |||
ECCR 100115 100115 | |||
I N T E R R U P T P R I O R I T Y | |||
====================================== | |||
LEVEL IDENT HARDWARE DEVICE NAME | |||
------------------------------------------ | |||
13 1 REAL TIME CLOCK 1 | |||
13 154 HDLC / MEGALINK 5 | |||
12 154 HDLC / MEGALINK 5 | |||
12 44 TERMINAL INTERFACE 5 | |||
12 45 TERMINAL INTERFACE 6 | |||
12 46 TERMINAL INTERFACE 7 | |||
12 47 TERMINAL INTERFACE 8 | |||
12 50 TERMINAL INTERFACE 9 | |||
12 51 TERMINAL INTERFACE 10 | |||
12 52 TERMINAL INTERFACE 11 | |||
12 53 TERMINAL INTERFACE 12 | |||
11 1 ST506 5" DISC CONTR. 1 | |||
11 21 FLOPPY & STREAMER 5 & 8 1 | |||
10 44 TERMINAL INTERFACE 5 | |||
10 45 TERMINAL INTERFACE 6 | |||
10 46 TERMINAL INTERFACE 7 | |||
10 47 TERMINAL INTERFACE 8 | |||
10 50 TERMINAL INTERFACE 9 | |||
10 51 TERMINAL INTERFACE 10 | |||
10 52 TERMINAL INTERFACE 11 | |||
10 53 TERMINAL INTERFACE 12 | |||
=== END OF INVESTIGATION === | |||
=== NO ERRORS DETECTED === | |||
</pre></div> | |||
=== OUTPUT FROM TEST PROGRAM 'INSTRUCTION' === | |||
<div class="mw-code"><pre> | |||
INSTRUCTION - Version: C03 - 1988-03-04 | |||
CPU type.............: ND-100/CX upgraded for 16 PITs | |||
Floating format......: 48 bits | |||
Memory management....: MMS-2 | |||
Cache................: Manually disabled | |||
ALD register content.: 20500B | |||
Cpu cycle............: Fast | |||
TPE>run | |||
=== Running Tests on Level 1 === | |||
=== Argument instructions === End of test === | |||
=== Memory reference instructions === End of test === | |||
=== Sequencing instructions === End of test === | |||
=== Register instructions === End of test === | |||
=== Bit instructions === End of test === | |||
=== Shift instructions === End of test === | |||
=== 48 bits floating instructions === End of test === | |||
=== Privileged instructions === End of test === | |||
=== Byte instructions === End of test === | |||
=== Physical memory instructions === End of test === | |||
=== Binary coded decimal instructions === End of test === | |||
=== Cx instructions === End of test === | |||
=== Stack instructions === End of test === | |||
=== Segment instructions === End of test === | |||
=== Internal interrupts === End of test === | |||
</pre></div> | |||
=== OUTPUT FROM TEST PROGRAM 'PAGING' === | |||
<div class="mw-code"><pre> | |||
PAGING - Version: C02 - 1988-03-01 | |||
CPU type.............: ND-100/CX upgraded for 16 PITs | |||
Floating format......: 48 bits | |||
Memory management....: MMS-2 | |||
Cache................: Manually disabled | |||
ALD register content.: 20500B | |||
Correct ECO level for running SINTRAN-III VSX/K | |||
TPE>run | |||
Test number(s) (1 to 11 dec): All-tests | |||
Run mode: Single pass. Abort after 10 errors. | |||
Test started. Time: 1979.01.01 20:27:29 | |||
1. PAGETABLE AREA as MEMORY (Address and data bits) - End of test - | |||
2. PAGING CONTROL REGISTERS on all levels - End of test - | |||
3. PGU/WIP bits for all PITS and ENTRIES - End of test - | |||
4. ALTERNATIVE PIT usage on all levels - End of test - | |||
5. RING VIOLATION interrupt on all levels - End of test - | |||
6. PAGE FAULT interrupt - End of test - | |||
7. READ PROTECT VIOLATION interrupt - End of test - | |||
8. WRITE PROTECT VIOLATION interrupt - End of test - | |||
9. FETCH PROTECT VIOLATION interrupt - End of test - | |||
10. PRIVILEGED INSTRUCTION interrupt - End of test - | |||
11. PHYSICAL ADDRESS generation - End of test - | |||
Test finished. Time: 1979.01.01 20:35:26 | |||
(Note: first time it was run it hang at #4) | |||
</pre></div> | |||
=== OUTPUT FROM TEST PROGRAM 'CONFIGURATION' AFTER HDLC Controller was added === | |||
<div class="mw-code"><pre> | |||
(Only listing changes) | |||
FIRST LAST I D E N T C O D E S LOG. | |||
HARDWARE DEVICE NAME DEVNO DEVNO LEV10 LEV11 LEV12 LEV13 DEVNO | |||
------------------------------------------------------------------------------- | |||
HDLC REMOTE LOAD 1 1604 1607 | |||
HDLC / MEGALINK 1 1640 1657 150 150 1360 | |||
I N T E R R U P T P R I O R I T Y | |||
====================================== | |||
LEVEL IDENT HARDWARE DEVICE NAME | |||
------------------------------------------ | |||
13 150 HDLC / MEGALINK 1 | |||
12 150 HDLC / MEGALINK 1 | |||
Original settings on Megalink card | |||
* TH1=6 <= Baud rate 9.6 kbps | |||
* TH2=1 <= Autoload 1 - device address 1604-1607 (octal) <= Logical device no 1370 | |||
* TH3=4 <= megalink #5 - device address 1740-1757 (octal) - ident code 154 (octal) | |||
* SW 26G <= 110011 = Special 983 kbps, normal operation (6:on, 5:on, 4:off, 3:off, 2:on, 1:x - special 983 kbps, normal operation) | |||
* SW 13A <= 1000 = 4:x, 3:x, 2:off, 1:on - normal operation, BUSY enabled | |||
Changed settings | |||
TH3=0 <= Megalink #1 | |||
</pre></div> | |||
=== OUTPUT FROM TEST PROGRAM 'MEMORY' === | |||
<div class="mw-code"><pre> | |||
MEMORY - Version: D04 - 1988-02-01 | |||
Total memory size....: 2.000 Mbytes | |||
TPE>run | |||
AREA TESTED: 0.12-15.15 | |||
READ TEST ON PROGRAM PART === END OF TEST === | |||
ADDRESSES IN ADDRESSES === END OF TEST === | |||
WRITE/READ TEST (7 PATTERNS) === END OF TEST === | |||
RAPIDLY CHANGING ADDRESS BITS === END OF TEST === | |||
PARITY ERROR DETECTION === END OF TEST === | |||
WALK TEST (34 PATTERNS) === END OF TEST === | |||
</pre></div> | |||
=== OTHER TEST PROGRAMS === | |||
* HDLC-MEGALIN-D00 (HDLC-MEGALINK - Version: D00 - 1986-10-30) | |||
Validated both PIO and DMA successfully. | |||
* TERMINAL-ASY-F01 (TERMINAL-ASYNC - Version: F01 - 1987-09-01) | |||
Unable to find any way to do loopback test. I might need to re-configure to RS-232 as it may be Current-Loop | |||
== References == | == References == |
Latest revision as of 23:10, 3 October 2024
A ND-100 Satellite model 14 machine in RHansen's collection,
Hardware
Hardware in the machine is described in this section.
Even if its an ND-100 Satellite, it seems it uses the same chassis as the ND-110 Satellite. In this case its the Model 14 chassis.
A sales document with more details for the ND-110 Satellite can be found here http://norsk-data.com/library/libsales/ND-SID019-A1-NO.pdf
Cards
Slot | Part Number | PCB Number | Description | Print Version | ECO |
---|---|---|---|---|---|
8 TI | 322613 | PCB 3013 | 8 TERM IF | Print L | |
HDLC | |||||
FL+STR | 324012 | PCB 3112 | 8" + 5 1/4 FLOPPY | Print B | ECO J |
ST506 | 322671 | PCB 3041 | N-100 ST 506 DISK CONTR. | Print E | ECO ? |
DRAM | 322672 | PCB 3042 | ND100 2MBY RAM | Print B | ECO C |
MMS | 324107 | PCB 3104 | MEM-MAN II EX. Cach | Print E | ECO N |
CPU | 322663 | PCB 3033 | ND100 CPU | Print ? | ECO V (48Bits CX) |
Switch settings
CPU 3033 ALD=13 (Mass boot from 500) Console Speed =7 (9600bps)
Devices
- Floppy drive : 5 1/4" (potentially 1.2MB)
- Tape streamer : Tandberg TDC 3309
- Hard drive : MICROPOLIS 1325 (74 MB) - Unable to read drive/bad sectors. Head stuck, but could get ut unstuck by opening the drive and using a chop-stick like described here [1]
Mounted on Disc-board 1824B
Power Supply
- Wiener DN 01, 390 W
Connectors
Labels
On the devices
FLOPPY: ND 187-3464 STREAMER: ND 150-001021 TDC 3300 Series, TDC_3309 (partno ? 326112) (serialno ? 564323) DISK: Micropolis 1325 (S/N:6082010769 P/N:900525-09-BA) 74 MB formatted (https://www.micropolis.com/support/hard-drives/1325)
On the front of the cabinet (behind the front door)
- printed label above tape streamer / floppy drive
LOGNR 1064
- Norsk Data ID LABEL at the bottom
CAB./ASSY NO: 1.1 FUNCTION: SATELLITE 14 SYSTEM NO: 16796
TODO
- Some basic cleaning as the system has been standing since the 90's
- Document all serial and model numbers on devices.
- Image the MFM disk before attempting a boot. Template:Failed Drive unreadable.
- Heads was stuck, had to "unstuck" them using a chopstick ref https://www.pdp8online.com/rd53/rd53.shtml
- Using MFM_READ tool and the MFM emulator I tried to dump the disk, but was unsuccessful due to "Bad sectors" on (almost) all cylinders
- Tested using ND program DISK-MM (DISK Media Maintenance - Version: C03 - 1990-06-11)
- Connected the drive to another ND machine (ND-110 Compact) to run MFM test programs
- Reported "NOT ON CYLINDER" when the heads was stuck, but after it changed to "Address mismatch" - sadly no data can be retrieved at this point
- Doing seek-test shows that the heads move freely across all cylinders. Can see that because the disk is opened, and I can visually inspect the head movements.
- Check the power supply condition Template:In progress
History
- 2024-10-03: Trying to identify signals from the HDLC output connector using a scope to find clock signal, but was rather unsuccessful.. maybe I am not expected to see clean digital clock signals - all I could find was somewhat analog. I really need to find some description for where where TX +/- and send clock +/- is supposed to be on the connectors.
- 2024-10-03: Tried to get ASYNC terminals to work. Unable to find any way to do loopback test with valid results. I might need to re-configure to RS-232 as it may be Current-Loop. Maybe card is defect?
- 2024-10-03: Booted SINTRAN from the MFM HDD emulator. Managed to get MegaLink card to work with XMSG subsystem, but I first had to reconfigure the device address so it became MegaLink #1 (was #5 in the other machine)
- 2024-10-03: There was one free slot in the machine, marked HDLC. Moved over a MegaLink card from my other machine, and now I could boot from floppy. Ran test programs and things seeem ok. Still some strange results in CONFIGURE first time I run it.
- 2024-10-03: Tried to boot from floppy, but system just hung. Seemed like INTERRUPT or IDENT signals somehow got lost.
- 2024-10-03: Opened the keylock and managed to get power to the system. Inserted back all the cards, one by one, and no smoke signals. Got console access.
- 2024-08-18: Tried to image the MFM HDD, but failed - disk unreadable
- 2024-08-18: Started going through the system, documenting it and basic cleaning in preparation for getting it up.
- 2024-08-17: System donated to me from Håvard Sten
TEST PROGRAMS
OUTPUT FROM TEST PROGRAM 'CONFIGURE'
CONFIGURATION - Version: D05 - 1988-11-08 > RUN H A R D W A R E C O N F I G U R A T I O N ============================================= CPU type.............: ND-100/CX upgraded for 16 PITs Floating format......: 48 bits Memory management....: MMS-2 Cache................: Manually disabled ALD register content.: 20500B Total memory size....: 2.000 Mbytes FIRST LAST I D E N T C O D E S LOG. HARDWARE DEVICE NAME DEVNO DEVNO LEV10 LEV11 LEV12 LEV13 DEVNO ------------------------------------------------------------------------------- REAL TIME CLOCK 1 10 13 1 TERMINAL INTERFACE 1 300 307 == Identcode not checked == 1 TERMINAL INTERFACE 5 340 347 44 44 44 TERMINAL INTERFACE 6 350 357 45 45 45 TERMINAL INTERFACE 7 360 367 46 46 46 TERMINAL INTERFACE 8 370 377 47 47 47 ST506 5" DISC CONTR. 1 500 507 1 1224 TERMINAL INTERFACE 9 1300 1307 50 50 60 TERMINAL INTERFACE 10 1310 1317 51 51 61 TERMINAL INTERFACE 11 1320 1327 52 52 62 TERMINAL INTERFACE 12 1330 1337 53 53 63 FLOPPY & STREAMER 5 & 8 1 1560 1567 21 1145 HDLC REMOTE LOAD 1 1604 1607 HDLC / MEGALINK 5 1740 1757 154 154 1370 ECCR 100115 100115 I N T E R R U P T P R I O R I T Y ====================================== LEVEL IDENT HARDWARE DEVICE NAME ------------------------------------------ 13 1 REAL TIME CLOCK 1 13 154 HDLC / MEGALINK 5 12 154 HDLC / MEGALINK 5 12 44 TERMINAL INTERFACE 5 12 45 TERMINAL INTERFACE 6 12 46 TERMINAL INTERFACE 7 12 47 TERMINAL INTERFACE 8 12 50 TERMINAL INTERFACE 9 12 51 TERMINAL INTERFACE 10 12 52 TERMINAL INTERFACE 11 12 53 TERMINAL INTERFACE 12 11 1 ST506 5" DISC CONTR. 1 11 21 FLOPPY & STREAMER 5 & 8 1 10 44 TERMINAL INTERFACE 5 10 45 TERMINAL INTERFACE 6 10 46 TERMINAL INTERFACE 7 10 47 TERMINAL INTERFACE 8 10 50 TERMINAL INTERFACE 9 10 51 TERMINAL INTERFACE 10 10 52 TERMINAL INTERFACE 11 10 53 TERMINAL INTERFACE 12 === END OF INVESTIGATION === === NO ERRORS DETECTED ===
OUTPUT FROM TEST PROGRAM 'INSTRUCTION'
INSTRUCTION - Version: C03 - 1988-03-04 CPU type.............: ND-100/CX upgraded for 16 PITs Floating format......: 48 bits Memory management....: MMS-2 Cache................: Manually disabled ALD register content.: 20500B Cpu cycle............: Fast TPE>run === Running Tests on Level 1 === === Argument instructions === End of test === === Memory reference instructions === End of test === === Sequencing instructions === End of test === === Register instructions === End of test === === Bit instructions === End of test === === Shift instructions === End of test === === 48 bits floating instructions === End of test === === Privileged instructions === End of test === === Byte instructions === End of test === === Physical memory instructions === End of test === === Binary coded decimal instructions === End of test === === Cx instructions === End of test === === Stack instructions === End of test === === Segment instructions === End of test === === Internal interrupts === End of test ===
OUTPUT FROM TEST PROGRAM 'PAGING'
PAGING - Version: C02 - 1988-03-01 CPU type.............: ND-100/CX upgraded for 16 PITs Floating format......: 48 bits Memory management....: MMS-2 Cache................: Manually disabled ALD register content.: 20500B Correct ECO level for running SINTRAN-III VSX/K TPE>run Test number(s) (1 to 11 dec): All-tests Run mode: Single pass. Abort after 10 errors. Test started. Time: 1979.01.01 20:27:29 1. PAGETABLE AREA as MEMORY (Address and data bits) - End of test - 2. PAGING CONTROL REGISTERS on all levels - End of test - 3. PGU/WIP bits for all PITS and ENTRIES - End of test - 4. ALTERNATIVE PIT usage on all levels - End of test - 5. RING VIOLATION interrupt on all levels - End of test - 6. PAGE FAULT interrupt - End of test - 7. READ PROTECT VIOLATION interrupt - End of test - 8. WRITE PROTECT VIOLATION interrupt - End of test - 9. FETCH PROTECT VIOLATION interrupt - End of test - 10. PRIVILEGED INSTRUCTION interrupt - End of test - 11. PHYSICAL ADDRESS generation - End of test - Test finished. Time: 1979.01.01 20:35:26 (Note: first time it was run it hang at #4)
OUTPUT FROM TEST PROGRAM 'CONFIGURATION' AFTER HDLC Controller was added
(Only listing changes) FIRST LAST I D E N T C O D E S LOG. HARDWARE DEVICE NAME DEVNO DEVNO LEV10 LEV11 LEV12 LEV13 DEVNO ------------------------------------------------------------------------------- HDLC REMOTE LOAD 1 1604 1607 HDLC / MEGALINK 1 1640 1657 150 150 1360 I N T E R R U P T P R I O R I T Y ====================================== LEVEL IDENT HARDWARE DEVICE NAME ------------------------------------------ 13 150 HDLC / MEGALINK 1 12 150 HDLC / MEGALINK 1 Original settings on Megalink card * TH1=6 <= Baud rate 9.6 kbps * TH2=1 <= Autoload 1 - device address 1604-1607 (octal) <= Logical device no 1370 * TH3=4 <= megalink #5 - device address 1740-1757 (octal) - ident code 154 (octal) * SW 26G <= 110011 = Special 983 kbps, normal operation (6:on, 5:on, 4:off, 3:off, 2:on, 1:x - special 983 kbps, normal operation) * SW 13A <= 1000 = 4:x, 3:x, 2:off, 1:on - normal operation, BUSY enabled Changed settings TH3=0 <= Megalink #1
OUTPUT FROM TEST PROGRAM 'MEMORY'
MEMORY - Version: D04 - 1988-02-01 Total memory size....: 2.000 Mbytes TPE>run AREA TESTED: 0.12-15.15 READ TEST ON PROGRAM PART === END OF TEST === ADDRESSES IN ADDRESSES === END OF TEST === WRITE/READ TEST (7 PATTERNS) === END OF TEST === RAPIDLY CHANGING ADDRESS BITS === END OF TEST === PARITY ERROR DETECTION === END OF TEST === WALK TEST (34 PATTERNS) === END OF TEST ===
OTHER TEST PROGRAMS
- HDLC-MEGALIN-D00 (HDLC-MEGALINK - Version: D00 - 1986-10-30)
Validated both PIO and DMA successfully.
- TERMINAL-ASY-F01 (TERMINAL-ASYNC - Version: F01 - 1987-09-01)
Unable to find any way to do loopback test. I might need to re-configure to RS-232 as it may be Current-Loop
References
[4][Norsk Data library, Hardware]
[5][Book 2: ND-100 SATELLITE, Assembly Drawings]
[6][Book 2: ND-100 SATELLITE, Cable Info. Block & Wiring Diagrams]