NLZ - Revision history

TArntsen: Register notation uniformity fix

2013-03-21T08:48:48Z

← Older revision		Revision as of 08:48, 21 March 2013
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	\|Format=NLZ ''<scaling>''		\|Format=NLZ ''<scaling>''
	\|Code=151 400		\|Code=151 400
	\|Affected=(T), (A), (D)		\|Affected=T, A, D
	\|Architecture=[[ND-100]], [[ND-110 CPU\|ND-110]]		\|Architecture=[[ND-100]], [[ND-110 CPU\|ND-110]]
	}}		}}

TArntsen: Change example to use MAC comment syntax (% not ;)

2011-05-25T17:45:08Z

Change example to use MAC comment syntax (% not ;)

← Older revision		Revision as of 17:45, 25 May 2011
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	For 32-bit floating point operations NLZ works as described above, except that the T register is not affected. This can also be used to test for 48-bit vs. 32-bit CPUs. The method is described in {{ND-doc\|06.029.01}}<ref>{{ND-doc\|06.029.01}}</ref> p.72:		For 32-bit floating point operations NLZ works as described above, except that the T register is not affected. This can also be used to test for 48-bit vs. 32-bit CPUs. The method is described in {{ND-doc\|06.029.01}}<ref>{{ND-doc\|06.029.01}}</ref> p.72:

	SAT 0 ; Set T register to zero (INSTRUCTION-B test program uses 'COPY 0 DT')		SAT 0 % Set T register to zero (INSTRUCTION-B test program uses 'COPY 0 DT')
	SAA 1 ; Set A register bit one		SAA 1 % Set A register bit one
	NLZ 16 ; Normalize with scaling factor 16 decimal		NLZ 16 % Normalize with scaling factor 16 decimal
	; Test if T is changed (non-zero). If so, the CPU is 48-bit, otherwise it is 32-bit.		% Test if T is changed (non-zero). If so, the CPU is 48-bit, otherwise it is 32-bit.

	== References ==		== References ==

TArntsen: /* References */

2011-05-25T09:48:37Z

References

← Older revision		Revision as of 09:48, 25 May 2011
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	== References ==		== References ==
			<references/>
	*{{ND-doc\|06.014.02\|pages 120, 144, 146 and 240}}		*{{ND-doc\|06.014.02\|pages 120, 144, 146 and 240}}
	*{{ND-doc\|06.029.01\|page 70 and 72}}		*{{ND-doc\|06.029.01\|page 70 and 72}}

TArntsen: Describe how NLZ is used as standard method to test for 48-bit vs. 32-bit floating point

2011-05-25T09:47:09Z

Describe how NLZ is used as standard method to test for 48-bit vs. 32-bit floating point

← Older revision		Revision as of 09:47, 25 May 2011
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	The ND-100/110 can have a 48-bit floating point CPU (standard configuration) or a 32-bit floating point CPU (customer option).		The ND-100/110 can have a 48-bit floating point CPU (standard configuration) or a 32-bit floating point CPU (customer option).
	For 32-bit floating point operations NLZ works as described above, except that the T register is not affected.		For 32-bit floating point operations NLZ works as described above, except that the T register is not affected. This can also be used to test for 48-bit vs. 32-bit CPUs. The method is described in {{ND-doc\|06.029.01}}<ref>{{ND-doc\|06.029.01}}</ref> p.72:

			SAT 0 ; Set T register to zero (INSTRUCTION-B test program uses 'COPY 0 DT')
			SAA 1 ; Set A register bit one
			NLZ 16 ; Normalize with scaling factor 16 decimal
			; Test if T is changed (non-zero). If so, the CPU is 48-bit, otherwise it is 32-bit.

	== References ==		== References ==

TArntsen: Typo: floting->floating

2010-07-01T10:06:56Z

Typo: floting->floating

← Older revision		Revision as of 10:06, 1 July 2010
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	{{main\|32-bit floating point}}		{{main\|32-bit floating point}}

	The ND-100/110 can have a 48-bit floating point CPU (standard configuration) or a 32-bit ~~floting~~ point CPU (customer option).		The ND-100/110 can have a 48-bit floating point CPU (standard configuration) or a 32-bit floating point CPU (customer option).
	For 32-bit floating point operations NLZ works as described above, except that the T register is not affected.		For 32-bit floating point operations NLZ works as described above, except that the T register is not affected.

TArntsen: Spellfix: Arcitecture -> Architecture

2009-08-03T13:35:24Z

Spellfix: Arcitecture -> Architecture

← Older revision		Revision as of 13:35, 3 August 2009
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	\|Code=151 400		\|Code=151 400
	\|Affected=(T), (A), (D)		\|Affected=(T), (A), (D)
	\|~~Arcitecture~~=[[ND-100]], [[ND-110 CPU\|ND-110]]		\|Architecture=[[ND-100]], [[ND-110 CPU\|ND-110]]
	}}		}}

TArntsen: Reduced and slightly reworded subheader, for clarity

2009-08-03T13:21:20Z

Reduced and slightly reworded subheader, for clarity

← Older revision		Revision as of 13:21, 3 August 2009
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	== ~~ND-100~~ 32-bit floating point ~~CPU~~ ==		==== NLZ on 32-bit floating point CPUs ====
	{{main\|32-bit floating point}}		{{main\|32-bit floating point}}

TArntsen: Clarify 48-bit FP/32-bit FP

2009-07-29T10:29:15Z

Clarify 48-bit FP/32-bit FP

← Older revision		Revision as of 10:29, 29 July 2009
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	\|Format=NLZ ''<scaling>''		\|Format=NLZ ''<scaling>''
	\|Code=151 400		\|Code=151 400
	\|Affected=(T), (A) ~~and~~ (D)		\|Affected=(T), (A), (D)
	\|Arcitecture=[[ND-100]], [[ND-110 CPU\|ND-110]]		\|Arcitecture=[[ND-100]], [[ND-110 CPU\|ND-110]]
	}}		}}

	'''NLZ''' is an assembly instruction. It converts the number in the [[A register]] to a standard form floating number in the [[floating point accumulator]] (A and D registers), using the ''scaling'' of the NLZ instruction as a scaling factor.		'''NLZ''' is an assembly instruction. It converts the number in the [[A register]] to a standard form [[48-bit floating point]] number in the [[floating point accumulator]] (T, A and D registers), using the ''scaling'' of the NLZ instruction as a scaling factor.

	The ''scaling'' is given to the conversion of -128 to 127 (approximately 10<sup>-39</sup> to 10<sup>39</sup>).		The ''scaling'' is given to the conversion of -128 to 127 (approximately 10<sup>-39</sup> to 10<sup>39</sup>).
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	== ND-~~110 48~~-bit floating point CPU ==		== ND-100 32-bit floating point CPU ==
	{{main\|48-bit floating point}}		{{main\|32-bit floating point}}

	The ND-110 can have a 48-bit floating point CPU. In the 48-bit floating point CPU a further register (T) and memory location ([[ea]] + 2) are used. In this case, the [[T register]] is linked to location ea, A to ea + 1 and D to ea + 2.

			The ND-100/110 can have a 48-bit floating point CPU (standard configuration) or a 32-bit floting point CPU (customer option).
			For 32-bit floating point operations NLZ works as described above, except that the T register is not affected.

	== References ==		== References ==
	*{{ND-doc\|06.014.02\|~~page~~ 144 and 240}}		*{{ND-doc\|06.014.02\|pages 120, 144, 146 and 240}}
	*{{ND-doc\|06.029.01\|page 70 and 72}}		*{{ND-doc\|06.029.01\|page 70 and 72}}


	[[Category:ND-100 instructions]]		[[Category:ND-100 instructions]]

Mike: refrase

2009-04-05T16:44:34Z

refrase

← Older revision		Revision as of 16:44, 5 April 2009
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	}}		}}

	'''NLZ''' is an instruction ~~on the ND platform~~. It converts the number in the [[A register]] to a standard form floating number in the [[floating point accumulator]] (A and D registers), using the ''scaling'' of the NLZ instruction as a scaling factor.		'''NLZ''' is an assembly instruction. It converts the number in the [[A register]] to a standard form floating number in the [[floating point accumulator]] (A and D registers), using the ''scaling'' of the NLZ instruction as a scaling factor.

	The ''scaling'' is given to the conversion of -128 to 127 (approximately 10<sup>-39</sup> to 10<sup>39</sup>).		The ''scaling'' is given to the conversion of -128 to 127 (approximately 10<sup>-39</sup> to 10<sup>39</sup>).

Mike: Adopt to new format in template, +"ND-110 48-bit floating point CPU"

2009-04-04T05:35:41Z

Adopt to new format in template, +"ND-110 48-bit floating point CPU"

← Older revision		Revision as of 05:35, 4 April 2009
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	\|Code=151 400		\|Code=151 400
	\|Affected=(T), (A) and (D)		\|Affected=(T), (A) and (D)
			\|Arcitecture=[[ND-100]], [[ND-110 CPU\|ND-110]]
	}}		}}

	'''NLZ''' is an instruction on the ND platform. It converts the number in the [[A register]] to a standard form floating number in [[~~the~~ floating accumulator]], using the ''scaling'' of the NLZ instruction as a scaling factor.		'''NLZ''' is an instruction on the ND platform. It converts the number in the [[A register]] to a standard form floating number in the [[floating point accumulator]] (A and D registers), using the ''scaling'' of the NLZ instruction as a scaling factor.

			The ''scaling'' is given to the conversion of -128 to 127 (approximately 10<sup>-39</sup> to 10<sup>39</sup>).

	For integers, a scaling factor of +16<sub><small>10</small></sub> will give a floating point number with the same value as the integer. A larger scaling factor will result in a higher floating point number. Because of the single precision fixed point number, the [[D register]] will be cleared.		For integers, a scaling factor of +16<sub><small>10</small></sub> will give a floating point number with the same value as the integer. A larger scaling factor will result in a higher floating point number. Because of the single precision fixed point number, the [[D register]] will be cleared.


	== Example ==		== Example ==
	*NLZ+20 (''code 151420'') Convert from integer to floating point.		*NLZ+20 (''code 151420'') Convert from integer to floating point.

	== ~~Sources~~ ==
	*{{ND-doc\|06.014.02\|~~Page~~ 144 and 240}}		== ND-110 48-bit floating point CPU ==
			{{main\|48-bit floating point}}

			The ND-110 can have a 48-bit floating point CPU. In the 48-bit floating point CPU a further register (T) and memory location ([[ea]] + 2) are used. In this case, the [[T register]] is linked to location ea, A to ea + 1 and D to ea + 2.


			== References ==
			*{{ND-doc\|06.014.02\|page 144 and 240}}
			*{{ND-doc\|06.029.01\|page 70 and 72}}

	[[Category:ND-100 instructions]]		[[Category:ND-100 instructions]]