FSB - Revision history

TArntsen: Improved and corrected

2010-07-01T09:58:55Z

Improved and corrected

← Older revision		Revision as of 09:58, 1 July 2010
Line 4:		Line 4:
	\|Format=FSB ''<[[ND-100 addressing modes\|addr. mode]]> <[[displacement\|disp.]]>''		\|Format=FSB ''<[[ND-100 addressing modes\|addr. mode]]> <[[displacement\|disp.]]>''
	\|Code=104 000		\|Code=104 000
	\|Affected=T~~:=(ea)~~ A~~=(ea+1)~~ D~~=(ea+2)~~		\|Affected=T A D, TG
	\|Architecture=[[ND-100]], [[ND-110 CPU\|ND-110]]		\|Architecture=[[ND-100]], [[ND-110 CPU\|ND-110]]
	}}		}}

	'''~~FAD~~''' is an assembly instruction. The contents of the [[effective address]] and the following one or two locations are subtracted from the [[floating accumulator]].		'''FSB''' is an assembly instruction. The contents of the [[effective address]] and the following one or two locations are subtracted from the [[floating accumulator]]. The result is in the floating accumulator.

	On 32-bit hardware only registers A and D are used, and two address locations instead of three~~. In this case, the A register is linked~~		On 32-bit floating point hardware only registers '''A''' and '''D''' are used, and two address locations instead of three.
	~~to (ea) and the D register to (ea+1)~~.

	== Flags affected ==		== Flags affected ==

TArntsen: Add 'Flags affected' subsection

2010-07-01T09:29:00Z

Add 'Flags affected' subsection

← Older revision		Revision as of 09:29, 1 July 2010
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	On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked		On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked
	to (ea) and the D register to (ea+1).		to (ea) and the D register to (ea+1).

			== Flags affected ==
			The [[rounding indicator]] for floating point operations ('''TG''', sometimes called just '''G''') may be set by this instruction.

	== References ==		== References ==

TArntsen: FSB instruction

2010-07-01T09:10:09Z

FSB instruction

New page

{{InstructionBox
|Mnemonic=FSB
|Description=Subtract from floating accumulator
|Format=FSB ''<[[ND-100 addressing modes|addr. mode]]> <[[displacement|disp.]]>''
|Code=104 000
|Affected=T:=(ea) A=(ea+1) D=(ea+2)
|Architecture=[[ND-100]], [[ND-110 CPU|ND-110]]
}}

'''FAD''' is an assembly instruction. The contents of the [[effective address]] and the following one or two locations are subtracted from the [[floating accumulator]].

On 32-bit hardware only registers A and D are used, and two address locations instead of three. In this case, the A register is linked
to (ea) and the D register to (ea+1).

== References ==
*{{ND-doc|06.014.02|Page 3-22}}
*{{ND-doc|06.029.01|Pages 68 and 72}}
[[Category:ND-100 instructions]]