View source for 3095

[[Image:ND110-CPU-board-component.jpg | thumb | ND-110 CX CPU board, component side]]
[[Image:ND110-CPU-board-solder.jpg | thumb | ND-110 CX CPU board, solder side]]
'''3095''' is the second [[ND-110 CPU]] board. The first version was numbered [[3090]]. It contains the CPU, bus arbitration logic, memory control, cache memory and other subsystems, including the Real time clock and the I/O for the serial console.
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==Introduction==
The ND-110 is an improvement over the ND-100 in a number of areas.
* Size. The CPU, the Memory Management System, cache memory and operator panel processor is combined on one single board.
* New technology. The CPU is constructed by a gate-array. The CPU concists of three VLSI gate arrays, RMIC, RMAC and BUFALU.
* New cache memory strategy. The first micro instruction word of a macroinstruction is stored in cache memory.
* Address arithmetic. Address arithmetic is performed in the RMAC gate array, not by the micro code as in ND-100.
* The interrupt system. Unlike the ND-100 CPU, the ND-110/CX CPU handles synchronous interrupts as traps., a bit like ND-500 does.
* The Control Store. The control store is based on fast read/write ram instead of prom. At power up the memory is initialised from two 8 kbyte EPROMs. The control store can be read or modified by program.
* Control logic and timing. Much of the control and timing logic have been moved into PAL chips. The main crystal oscillator is now a 39.3216 MHz oscillator. It is used for the nano-sequencer, the CPU-clock, the bus arbiter, the real time clock and the console UART. The nano-sequencer is a four bit state machine used for timing and control.
* Power consumption. The power consumption was reduced from 90 watts to 60. {{Citation needed}}

==New instructions ==

* [[TRA]] CS - Reads 16 control storage bits into the A-register. The X-register contains the store address.
* [[TRR]] CS - Writes the A-register into 16 control store bits. The X-register contains the control store address.
* [[TRR]] CILP - Cache inhibit individual page.
* [[VERSN]] - Reads version numbers of print and micro program.
* [[SETPT]] - Set page tables.
* [[CLEPT]] - Clear page tables.
* [[CLNREENT]] - Clear non re-entrant pages.
* [[CHREENTPAGES]] - Change page tables.
* [[CLEPU]] - Clear page tables and collect PGU information.
* [[WGLOB]] - Initialize global pointers.
* [[RGLOB]] - Examine global pointers.
* [[INSPL]] - Insert page in page list.
* [[REMPL]] - Remove page from page list.
* [[CNREK]] - Clear non re-entrant pages.
* [[CLPT]] - Clear segment from page tables.
* [[ENPT]] - Enter segment in page tables.
* [[REPT]] - Enter re-entrant segment in page tables.
* [[LBIT]] - Load single bit accumulator (K) with logical memory bit.
* [[SBITP]] - Store single bit accumulator (K) in a physical memory bit.
* [[LBYTP]] - Load the A register with a single byte from physical memory.
* [[SBYTP]] - Store single byte in physical memory.
* [[TSETP]] - Test and set a physical memory word.
* [[RDUSP]] - Read a physical memory word without using cache.
* [[LASB]] - Load the A register with the contents of the segment-table bank (STBNK).
* [[SASB]] - Store the A register contents in the STBNK.
* [[LACB]] - Load the A register with the contents of the core map-table bank (CMBNK).
* [[SACB]] - Store the A register contents in the CMBNK.
* [[LXSB]] - Load the X register with the contents of the STBNK.
* [[LXCB]] - Load the X register with the contents of the CMBNK.
* [[SZSB]] - Store zero in the STBNK.
* [[SZCB]] - Store zero in the CMBNK.

== Reference ==

*{{ND-doc|06.026|(ND-06.026.01 rev A)}}

[[Category:ND-100 hardware]]